Regular Article
Adaptive Routing on the New Switch Chip for IBM SP Systems

https://doi.org/10.1006/jpdc.2001.1747Get rights and content

Abstract

The IBM RS/6000 SP is one of the most successful commercially available multicomputers. SP owes its success partially to the scalable, high bandwidth, low latency network. This paper describes the architecture of Switch2 switch chip, the recently developed third generation switching element which future IBM RS/6000 SP systems may be based on. Switch2 offers significant enhancements over the existing SP switch chips by incorporating advances in both VLSI technology and interconnection network research. One of the major new features of Switch2 is the incorporation of adaptive routing support into it. We describe the adaptive source routing architecture of the Switch2 chip which is a unique feature of this chip. The performance of the adaptive source routing and oblivious routing for a wide range of system characteristics and traffic patterns is evaluated. It is shown that adaptive source routing outperforms or performs comparably with oblivious routing. We propose two novel algorithms for generating adaptive routes specifications required for enabling the usage of adaptive source routing. A comparison between the cost of these two algorithms and the performance improvement obtained from using these algorithms are discussed. We also propose different output selection functions to be used in switching elements for implementing the adaptive routing. We evaluate and compare the performance of these selection functions and discover that the best selection functions for BMINs are not dependent on the traffic pattern, message size, or system size.

References (31)

  • P. Kermani et al.

    Virtual cut-through: A new computer communications switching technique

    Computer Networks

    (Sept. 1979)
  • B. Abali et al.

    Routing algorithms for IBM SP1

    Proceedings of the 1st International Workshop PCRCW

    (1994)
  • B. Abali

    A deadlock avoidance method for computer networks

    Proceedings of the 1st International Workshop on Communication and Architectural Support for Network-Based Parallel Computing (CANPC)

    (1997)
  • Y. Aydogan et al.

    Adaptive source routing in multistage interconnection networks

    Proceedings of the 10th Int. Parallel Processing Symp. (IPPS)

    (April 1996)
  • S. Badr et al.

    An optimal shortest-path routing policy for network computers with regular mesh connected topologies

    IEEE Trans. Comput.

    (1989)
  • M. Banikazemi, C. Stunkel, D. K. Panda, and, B. Abali, Adaptive routing in RS/6000 SP-like bidirectional multistage...
  • T.H. Cormen et al.

    Introduction to Algorithms

    (1991)
  • D.E. Culler et al.

    Parallel Computer Architecture: A Hardware-Software Approach

    (March 1998)
  • W.J. Dally

    Performance analysis of k-ary n-cube interconnection networks

    IEEE Trans. Comput.

    (June 1990)
  • W.J. Dally

    Virtual-channel flow control

    IEEE Trans. Parallel Distrib. Systems

    (March 1992)
  • W.J. Dally et al.

    Deadlock-free message routing multiprocessor interconnection networks

    IEEE Trans. Comput.

    (May 1987)
  • J. Duato

    Improving the efficiency of virtual channels with time dependent selection functions

    Parallel Arch. and Lang. Europe 92

    (1992)
  • J. Duato et al.

    Interconnection Networks: An Engineering Approach

    (1997)
  • W. Feng et al.

    Impact of selection functions on routing algorithm performance in multicomputer networks

    Proceedings of the 11th Int. Conf. Supercomputing

    (1997)
  • C.J. Glass et al.

    The turn model for adaptive routing

    J. Assoc. Comput. Machin.

    (1994)
  • Cited by (0)

    View full text