A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing

doi:10.1006/rtim.2001.0273

Real-Time Imaging

Volume 8, Issue 5, October 2002, Pages 345-356

https://doi.org/10.1006/rtim.2001.0273 Get rights and content

Abstract

In this article, we present a new reconfigurable parallel architecture oriented to video-rate computer vision applications. This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors P_ij. These processors are interconnected by means of a systolic 2D array of FPGA-based video-addressing units which allow video-rate links between any two processors in the net to overcome the associated restrictions in classic crossbar systems such as those which occur with butterfly connections. This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. This proposed open architecture allows the host to deal with final high-level interpretation tasks. The exchange of information between the linked processorsP_ij of the 2D net lies in the transfer of complete images, pixel by pixel, at video-rate. Therefore, any kind of processor satisfying such a requirement can be integrated. Furthermore, the whole architecture has been designed host-independent.

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Because of cost, lack of stability software support for parallel machines, multiprocessor image processing systems are not able to fulfill their promise. Another way of obtaining high performance in image processing applications is to use Digital Signal Processing (DSP) processors [2,3]. In contrast to standard microprocessors, DSP processors provide performance improvement while still maintaining a high-level programming model.
Nowadays embedded multimedia devices are designed for computationally intensive applications such as image processing in various multimedia systems. Image processing algorithms should be implemented on hardware platforms for improving the performance. Reconfigurable hardware implementation using Field Programmable Gate Arrays (FPGAs) provides low latency with high performance in real time applications. FPGAs offer the reprogrammability of an application specific solution while retaining the performance advantage. In real time applications as image sizes increase rapidly, only hardware systems must be used with low complex software. In this paper, main perspective of developing and implementing skeletonization algorithm as a part of computer vision, pattern recognition application is focused and presented. A simple algorithm to skeletonize the 2-D image using MATLAB is developed. An architecture and implementation of this skeletonization algorithm for 2-D gray scale images is proposed. For analyzing pixel values 3 × 3 windowing operator is used. The proposed architecture is tested for an image size of 8 × 8, but the approach presented in this paper can be used for images of any size (M × N), if the FPGA memory is sufficiently large. The implementation was carried out on Xilinx Vertex 5 board.
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