Let us consider a scheme that involves several registers and produces one output sequence. Based on some clocking mechanism, the registers go from one state to another, thereby producing an output bit. We can choose whether or not to synchronize these registers. In the second case, the output of the scheme will be more nonlinear than in the first case.
We will consider here registers whose clock is controlled by some events. The best studied case is the one of Linear Feedback Shift Registers (LFSR), but this concept could be applied also to Nonlinear Feedback Shift Registers (NLFSR).
So, the main idea here is that we have, for example, two LFSRs, say \(R_1\) and \(R_{ 2}\), and that the output of \(R_1\) will determine the clocking of \(R_{ 2}\). For example, if \(R_1\) outputs a 1, then clock \(R_{ 2}\) twice, and if \(R_1\) outputs a 0, then clock \(R_{ 2}\) three times. The output of the scheme could be the one of \(R_{ 2}\).
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References
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Fontaine, C. (2005). Clock-Controlled Generator. In: van Tilborg, H.C.A. (eds) Encyclopedia of Cryptography and Security. Springer, Boston, MA . https://doi.org/10.1007/0-387-23483-7_65
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