Definition:The Intel XScale micro-architecture is an implementation of the ARM V5TE architecture.
The XScale core supports both dynamic frequency and voltage scaling with a maximum frequency today in handheld devices of 624MHz (and increasing going forward). The design is a scalar, in-order single issue architecture with concurrent execution in 3 pipes that support out-of-order return. To support the frequency targets, a 7-stage integer pipeline is employed with dynamic branch prediction supplied to mitigate the cost of a deeper pipeline (see Figure 1).
In favour of memory access efficiency, the Intel XScale micro-architecture contains instruction and data caches (32KB each). Also, in order to hide memory latency the micro-architecture supports software issued prefetch capability coupled with advanced load and store buffering. Load buffering allows multiple data/cache lines request from the memory concurrently, thus reducing the data loading overhead. Similarly, store buffers combine...
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References
Seal, David “Advanced RISC Machines Architecture Reference Manual,” Prentice Hall, 1996.
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(2006). Intel® XScale® Micro-Architecture. In: Furht, B. (eds) Encyclopedia of Multimedia. Springer, Boston, MA. https://doi.org/10.1007/0-387-30038-4_111
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DOI: https://doi.org/10.1007/0-387-30038-4_111
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