Abstract
In this paper, we present algorithms, suitable for hardware implementation, for computation in the Jacobian of a hyperelliptic curve defined over GF(2n). We take curves of genus 3 and 6, designed by using 0.27-um CMOS gate array technology, and estimate the number of multiplication operations and the size and speed of hardware based on the proposed algorithm. It is shown that hardware for genus 6 curves computes an addition (resp. doubling) operation in 100 (resp. 29) clock cycles and can work at clock frequencies of up to 83 MHz We also compare a hyperelliptic curve cryptosystem with RSA and elliptic curve cryptosystems from the viewpoint of hardware implementation.
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Tamura, T., Sakurai, K., Matsumoto, T. (2000). A Hardware-Oriented Algorithm for Computing in Jacobians and Its Implementation for Hyperelliptic Curve Cryptosystems. In: Song, J. (eds) Information Security and Cryptology - ICISC’99. ICISC 1999. Lecture Notes in Computer Science, vol 1787. Springer, Berlin, Heidelberg. https://doi.org/10.1007/10719994_18
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DOI: https://doi.org/10.1007/10719994_18
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