Abstract
In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low power consumption applications. The elementary gates used are threshold logic gates (perceptrons). Simulations have been performed both with and without considering the delay on the wires. These simulations confirm that wires play a significant role, reducing the speed advantage of the parallel adder (over the serial one) from 4.5x to 2.2–2.4x. A promising result is that the speed of both adders improves more than 10x when migrating from 100nm to 70nm. The full adder based on threshold logic gates (used in the ripple carry adder) improves on previously known full adders, achieving 1.6fJ when operated at 200mV in 120nm CMOS. Finally, the speed of the parallel adder can be matched by the serial adder when operating at only 10–20% higher V dd , while still requiring less power and energy.
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References
ITRS: The International Technology Roadmap for Semiconductors (2004), http://public.itrs.net/
Beiu, V., Rückert, U., Roy, S., Nyathi, J.: On nanoelectronic architectural challenges and solutions. In: Proc. IEEE Conference on Nanotechnology, pp. 628–631 (2004)
Burr, J.B., Shott, J.: A 200 mV self-testing encoder/decoder using stanford ultra-low-power CMOS. In: Proc. IEEE International Solid-State Circuits Conference, pp. 84–85 (1994)
Lande, T.S., Wisland, D.T., Sæther, T., Berg, Y.: FLOGIC-floating-gate logic for low-power operation. In: Proc. International Conference on Electronics, Circuits, and Systems, vol. 2, pp. 1041–1044 (1996)
Kim, C.H., Soeleman, H., Roy, K.: Ultra-low-power DLMS adaptive filter for hearing aid applications. IEEE Trans. on VLSI Systems 11, 1058–1067 (2003)
Wentzloff, D.D., Calhoun, B.H., Min, R., Wang, A., Ickes, N., Chandrakasan, A.P.: Design considerations for next generation wireless power-aware microsensor nodes. In: Proc. International Conference on VLSI Design, pp. 361–367 (2004)
Ishibashi, K., Yamashita, T., Y, A., Minematsu, I., Fuji-moto, T.: A 9uW 50MHz 32b adder using a self-adjusted forward body bias in SoCs. In: Proc. International Solid-State Circuits Conference, vol. 1, pp. 116–119 (2003)
Soeleman, H., Roy, K., Paul, B.: Robust subthreshold logic for ultra-low power operation. IEEE Transactions on VLSI Systems 9, 90–99 (2001)
Paul, B.C., Raychowdhury, A., Roy, K.: Device optimization for digital subthreshold logic operation. IEEE Transactions on Electron Devices 52, 237–247 (2005)
Calhoun, B.H., Wang, A., Chandrakasan, A.: Device sizing for minimum energy operation in subthreshold circuits. In: Proc. IEEE Custom Integrated Circuits Conference, pp. 95–98 (2004)
Beiu, V., Quintana, J., Avedillo, M.: VLSI impl. of threshold logic: A comprehensive survey. IEEE Transactions on Neural Networks 14, 1217–1243 (2003)
Beiu, V.: Constructive threshold logic addition: A synopsis of the last decade. In: Kaynak, O., Alpaydın, E., Oja, E., Xu, L. (eds.) ICANN 2003 and ICONIP 2003. LNCS, vol. 2714, pp. 745–752. Springer, Heidelberg (2003)
Celinski, P., Al-Sarawi, S., Abbott, D., Cotofana, S., Vassiliadis, S.: Logical effort based design exploration of 64-bit adders using a mixed dynamic-cmos/threshold-logic approach. In: Proc. Annual Symposium on VLSI, pp. 127–132 (2004)
Aunet, S., Berg, Y., Tjore, O., Næss, Ø., Sæther, T.: Four-MOSFET floating-gate UV-programmable elements for multifunction binary logic. In: Proc. Multiconference on Systemics, vol. 3, pp. 141–144 (2001)
Aunet, S., Oelmann, B., Abdalla, S., Berg, Y.: Reconfigurable subthreshold CMOS perceptron. In: Proc. IEEE International Joint Conference on Neural Networks, pp. 1983–1988 (2004)
Sulieman, M., Beiu, V.: Characterization of a 16-bit threshold logic single electron technology adder. In: Proc. International Symposium on Circuits and Systems, pp. 681–684 (2004)
Beiu, V.: A novel highly reliable low-power nano architecture: When von Neumann augments Kolmogorov. In: Proc. Application-specific Systems, Architectures and Processors, pp. 167–178 (2004)
Iwamura, H., Akazawa, M., Amemiya, Y.: Single-electron majority logic circuits. IEICE Transactions on Electronics E18-C, 42–48 (1998)
Kogge, P., Stone, H.: A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers, 786–793 (1973)
Cao, Y., Sato, T., Orshansky, M., Sylvester, D., Hu, C.: New paradigm of predictive MOSFET and interconnect modeling for early circuit design. In: Proc. IEEE Custom Integrated Circuits Conference, 201–204 (2000), http://www-device.eecs.berkeley.edu/~ptm
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Beiu, V., Djupdal, A., Aunet, S. (2005). Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. In: Cabestany, J., Prieto, A., Sandoval, F. (eds) Computational Intelligence and Bioinspired Systems. IWANN 2005. Lecture Notes in Computer Science, vol 3512. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11494669_60
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DOI: https://doi.org/10.1007/11494669_60
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