Abstract
State verification is a more restricted problem than state identification, discussed in Chapter 2. As in state verification, we know the state diagram of the system under test. The difference is that we have an assumption about which state the system is currently in, and the objective is to check that this assumption is correct. The basic idea is that when testing a machine, we can give it an input sequence, and then use state verification to verify that the sequence took the machine under test to the expected state.
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© 2005 Springer-Verlag Berlin Heidelberg
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Björklund, H. (2005). 3 State Verification. In: Broy, M., Jonsson, B., Katoen, JP., Leucker, M., Pretschner, A. (eds) Model-Based Testing of Reactive Systems. Lecture Notes in Computer Science, vol 3472. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11498490_4
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DOI: https://doi.org/10.1007/11498490_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26278-7
Online ISBN: 978-3-540-32037-1
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