Abstract
In this article, we present two AES hardware architectures: one for ASICs and one for FPGAs. Both architectures utilize the similarities of encryption and decryption to provide a high throughput using only a relatively small area. The presented architectures can be used in a wide range of applications. The architecture for ASIC implementations is suited for full-custom as well as for semi-custom design flows. The architecture for the FPGA implementation does not require on-chip block RAMs and can therefore even be used for low-cost FPGAs.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
ARM Limited. AMBA 2.0 Specification (2001), http://www.arm.com/armtech/
Chodowiec, P., Gaj, K.: Very Compact FPGA Implementation of the AES Algorithm. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 319–333. Springer, Heidelberg (2003)
Chodowiec, P., Khuon, P., Gaj, K.: Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining. In: Symposium on Field Programmable Gate Arrays – FPGA 2001, pp. 94–102. ACM Press, New York (2001)
Daemen, J., Rijmen, V.: The Design of Rijndael. Springer, Heidelberg (2002)
Dandalis, A., Prasanna, V., Rolim, J.: A Comparative Study of Performance of AES Final Candidates Using FGPAs (2000), http://csrc.nist.gov/CryptoToolkit/aes/round2/conf3/aes3agenda.html
Fischer, V., Drutarovský, M.: Two Methods of Rijndael Implementation in Reconfigurable Hardware. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 77–92. Springer, Heidelberg (2001)
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Mangard, S., Aigner, M., Dominikus, S.: A Highly Regular and Scalable AES Hardware Architecture. IEEE Transactions on Computers 52, 483–491 (2003)
McLoone, M., McCanny, J.V.: High Performance Single-Chip FPGA Rijndael Algorithm Implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 65–76. Springer, Heidelberg (2001)
National Institute of Standards and Technology. Federal Information Processing Standard 197, The Advanced Encryption Standard, AES (2001), http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
Pramstaller, N., Gürkaynak, F.K., Haene, S., Kaeslin, H., Felber, N., Fichtner, W.: Towards an AES Crypto-chip Resistant to Differential Power Analysis. In: Proccedings of ESSCIRC 2004 (2004) (to appear)
Rudra, A., Dubey, P.K., Jutla, C.S., Kumar, V., Rao, J.R., Rohatgi, P.: Efficient Rijndael Encryption Implementation with Composite Field Arithmetic. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 171–184. Springer, Heidelberg (2001)
Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A Compact Rijndael Hardware Architecture with S-Box Optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239–254. Springer, Heidelberg (2001)
Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: Proceedings of ESSCIRC 2002 (2002)
Tiri, K., Verbauwhede, I.: Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 125–136. Springer, Heidelberg (2003)
Weeks, B., Bean, M., Rozylowicz, T., Ficke, C.: Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms (2000), http://csrc.nist.gov/encryption/aes/round2/NSA-AESfinalreport.pdf
Wolkerstorfer, J.: An ASIC implementation of the AES-MixColumn operation. In: Proceedings of Austrochip 2001 (October 2001)
Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES S-Boxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol. 2271, p. 67. Springer, Heidelberg (2002)
Wu, S.-Y., Lu, S.-C., Laih, C.-S.: Design of AES Based on Dual Cipher and Composite Field. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol. 2964, pp. 25–38. Springer, Heidelberg (2004)
Xilinx Incorporated. Silicon Solutions — Virtex Series FPGAs, http://www.xilinx.com/products/
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Pramstaller, N., Mangard, S., Dominikus, S., Wolkerstorfer, J. (2005). Efficient AES Implementations on ASICs and FPGAs. In: Dobbertin, H., Rijmen, V., Sowa, A. (eds) Advanced Encryption Standard – AES. AES 2004. Lecture Notes in Computer Science, vol 3373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11506447_9
Download citation
DOI: https://doi.org/10.1007/11506447_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26557-3
Online ISBN: 978-3-540-31840-8
eBook Packages: Computer ScienceComputer Science (R0)