Skip to main content
SpringerLink
Log in
Book cover

International Workshop on Embedded Computer Systems

SAMOS 2005: Embedded Computer Systems: Architectures, Modeling, and Simulation pp 122–131Cite as

Formal Specification of a Protocol Processor

  • Conference paper

  • 714 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3553))

Abstract

To ensure the correctness of functional and temporal properties of modern network hardware devices is becoming increasingly challenging because the growing complexity and demanding time-to-market requirements. In this paper we address the problem by deriving a TACO protocol processor model in the formal framework of Timed Action Systems. Formal methods offer a prominent approach to specify, design, and verify such devices with the benefits of a rigorous mathematical basis. The derivation demonstrates the capability of preserving correctness when considering an important hardware design decision.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Back, R.J., Sere, K.: From Modular Systems to Action Systems. In: Naftalin, M., Bertrán, M., Denvir, T. (eds.) FME 1994. LNCS, vol. 873, Springer, Heidelberg (1994)

    Google Scholar 

  2. Back, R.J., Kurki-Suonio, R.: Decentralization of Process Nets with Centralized Control. In: Procs. of the 2nd ACM SIGACT-SIGOPS Symp. on Principles of Distributed Computing, pp. 131–142 (1983)

    Google Scholar 

  3. Dijkstra, E.W.: A Discipline of Programming. Prentice-Hall International, Englewood Cliffs (1976)

    MATH  Google Scholar 

  4. Seceleanu, T.: Systematic Design of Synchronous Digital Circuits. PhD thesis, Turku Centre for Computer Science (2001)

    Google Scholar 

  5. Plosila, J.: Self-Timed Circuit Design - The Action System Approach. PhD thesis, University of Turku (1999)

    Google Scholar 

  6. Westerlund, T., Plosila, J.: Formal Timing Model for Hardware Components. In: Proceedings of the 22nd NORCHIP Conference, Norway, pp. 293–296 (2004)

    Google Scholar 

  7. Virtanen, S.: A Framework for Rapid Design and Evaluation of Protocol Processors. PhD thesis, University of Turku (2004)

    Google Scholar 

  8. Back, R.J., Martin, A.J., Sere, K.: Specifying the Caltech Asynchronous Microprocessor. Sci. Comput. Program. 26, 79–97 (1996)

    Article  MATH  Google Scholar 

  9. Plosila, J., Sere, K.: Action Systems in Pipelined Processor Design. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 156–166 (1997)

    Google Scholar 

  10. He, J., Turner, K.J.: Specification and verification of synchronous hardware using LOTOS. In: Proc. Formal Methods for Protocol Engineering and Distributed Systems, pp. 295–312 (1999)

    Google Scholar 

  11. Kim, H., Beerel, P.A.: Relative timing based verification of timed circuits and systems. In: Proc. International Workshop on Logic Synthesis (1999)

    Google Scholar 

  12. Stevens, K., Ginosar, R., Rotem, S.: Relative Timing. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 208–218 (1999)

    Google Scholar 

  13. Rotem, S., Stevens, K., Ginosar, R., Beerel, P., Myers, C., Yun, K., Kol, R., Dike, C., Roncken, M., Agapiev, B.: RAPPID: An Asynchronous Instruction Length Decoder. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 60–70 (1999)

    Google Scholar 

  14. Back, R.J., von Wright, J.: Refinement Calculus: A Systematic Introduction. Springer, Heidelberg (1998)

    MATH  Google Scholar 

  15. Back, R.J., von Wright, J.: Trace Refinement of Action Systems. In: International Conference on Concurrency Theory, pp. 367–384 (1994)

    Google Scholar 

  16. Westerlund, T., Plosila, J.: Towards a Timed Refinement Calculus for Hardware Systems. Technical Report TR669, Turku Centre for Computer Science (2004)

    Google Scholar 

  17. Corporaal, H.: Microprocessor Architectures - from VLIW to TTA. John Wiley and Sons Ltd., Chichester (1998)

    Google Scholar 

  18. Tabak, D., Lipovski, G.J.: MOVE Architecture in Digital Controllers. IEEE Transactions on Computers 29, 180–190 (1980)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Turku Centre for Computer Science, Lemminkäisenkatu 14 A, FIN-20520, Turku, Finland

    Tomi Westerlund

  2. Department of Information Technology, University of Turku, Lemminkäisenkatu 14 A, FIN-20520, Turku, Finland

    Tomi Westerlund & Juha Plosila

Authors
  1. Tomi Westerlund
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Juha Plosila
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Computer Systems, Tampere University of Technology, P.O. Box 553, FI-33101, Tampere, Finland

    Timo D. Hämäläinen

  2. Computer Systems Architecture Group, University of Amsterdam, The Netherlands

    Andy D. Pimentel

  3. Tampere University of Technology, Korkeakoulunkatu 1, 33720, Tampere, Finland

    Jarmo Takala

  4. Computer Engineering Lab, TUDelft., Postbus 5031, 2600, Delft, GA, The Netherlands

    Stamatis Vassiliadis

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Westerlund, T., Plosila, J. (2005). Formal Specification of a Protocol Processor. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_14

Download citation

  • DOI: https://doi.org/10.1007/11512622_14

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-26969-4

  • Online ISBN: 978-3-540-31664-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation