Abstract
High-end microprocessors achieve their performance as a result of adding more features and therefore increasing their complexity. In this paper we present DDM-CMP, a Chip-Multiprocessor using the Data-Driven Multithreading execution model.
As a proof-of-concept we present a DDM-CMP configuration with the same hardware budget as a high-end processor. In that budget we implement four simpler CPUs, the TSUs, and the interconnection network. An estimation of DDMCMP performance for the execution of SPLASH-2 kernels shows that, for the same clock frequency, DDM-CMP achieves a speedup of 2.6 to 7.6 compared to the high-end processor. A lower frequency configuration, which is more powerefficient, still achieves high speedup (1.1 to 3.3). These encouraging results lead us to believe that the proposed architecture has a significant benefit over traditional designs.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Palacharla, S., Jouppi, N., Smith, J.: Complexity Effective Superscalar Processors. In: Proc. of the 24th ISCA, pp. 206–218 (1997)
Olukotun, K., et al.: The Case for a Single Chip Multiprocessor. In: Proc. of the 7th ASPLOS, pp. 2–11 (1996)
Silas, I., et al.: System-Level Validation of the Intel(r) Pentium(r) M Processor. Intel Technology Journal 7 (2003)
Agarwal, V., et al.: Clock rate versus IPC: The end of the Road for Conventional Microarchitectures. In: Proc. of the 27th ISCA, pp. 248–259 (2000)
Hammond, L., et al.: The Stanford Hydra CMP. IEEE Micro 20, 71–84 (2000)
Barroso, L., et al.: Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In: Proc. of the 27th ISCA, pp. 282–293 (2000)
Taylor, M., et al.: Evaluation of the Raw Microprocessor: An Exposed Wire Delay Architecture for ILP and Streams. In: Proc. of the 31st ISCA, pp. 2–13 (2004)
Kalla, R., Sinharoy, B., Tendler, M.: IBM POWER5 Chip: A Dual-Core Multithreaded Processor. IEEE Micro 24, 40–47 (2004)
Kongetira, P.: A 32-way Multithreaded SPARC Processor. In: Proc. of Hot Chips 2004 (2004)
Kyriacou, C., Evripidou, P., Trancoso, P.: Data Driven Multithreading Using Conventional Microprocessors. Technical Report TR-05-4, University of Cyprus (2005)
Evripidou, P., Kyriacou, C.: Data driven network of workstations (D2NOW). J. UCS 6, 1015–1033 (2000)
XILINX: Virtex-II Pro and Virtex-II Pro X FPGA User Guide. Version 3.0 (2004)
Evripidou, P.: D3-machine: A Decoupled Data Driven Multithreaded architecture with variable resolution support. Parallel Computing 27, 1015–1033 (2001)
Evripidou, P., Gaudiot, J.: A decoupled graph/computation data-driven architecture with variable resolution actors. In: Proc. of ICPP 1990, pp. 405–414 (1990)
Kyriacou, C.: Data Driven Multithreading using Conventional Control Flow Microprocessors. PhD dissertation, University of Cyprus (2005)
Kyriacou, C., Evripidou, P., Trancoso, P.: CacheFlow: A Short-Term Optimal Cache Management Policy for Data Driven Multithreading. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds.) Euro-Par 2004. LNCS, vol. 3149, pp. 561–570. Springer, Heidelberg (2004)
IBM Microelectronics Division: The PowerPC 405(tm) Core (1998)
The BlueGene/L Team: An Overview of the BlueGene/L Supercomputer. In: Proc. of the 2002 ACM/IEEE supercomputing, pp. 1–28 (2002)
Intel: Intel Microprocessor Quick Reference Guide (2004), http://www.intel.com/pressroom/kitsquickreffam.htm
PCL: The Performance Counter Library Version 2.2 (2003)
Woo, S., et al.: The SPLASH-2 Programs: Characterization and Methodological Considerations. In: Proc. of 22nd ISCA, pp. 24–36 (1995)
Topelt, B., Schuhmann, D., Volkel, F.: The mother of all CPU charts Part 2 (2004), http://www6.tomshardware.com/cpu/20041221/index.html
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Stavrou, K., Evripidou, P., Trancoso, P. (2005). DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_39
Download citation
DOI: https://doi.org/10.1007/11512622_39
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26969-4
Online ISBN: 978-3-540-31664-0
eBook Packages: Computer ScienceComputer Science (R0)