Abstract
The knowledge of internal structures of the cache-memory hierarchy and its performance is very important in modern computer systems. Therefor, this paper introduces a mathematical model that describes the transition between Level 1 and Level 2 cache of current processors. The theoretical predictions are proved by measurements for two Intel CPUs and an UltraSparc II system.
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Krietemeyer, M., Versick, D., Tavangarian, D. (2006). A Mathematical Model for the Transitional Region Between Cache Hierarchy Levels. In: Böhme, T., Larios Rosillo, V.M., Unger, H., Unger, H. (eds) Innovative Internet Community Systems. IICS 2004. Lecture Notes in Computer Science, vol 3473. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11553762_18
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DOI: https://doi.org/10.1007/11553762_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28880-0
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