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Compact Static Power Model of Complex CMOS Gates

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3728))

Abstract

We present a compact model to estimate quickly and accurately the leakage power in CMOS nanometer Integrated Circuits (ICs). The model has similar accuracy than SPICE and represents an important improvement with respect to previous works. It has been developed to be used for fast and accurate estimation and optimization of the standby power dissipated by large circuits.

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References

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Author information

Authors and Affiliations

  1. Electronic Technology Group, Universitat de les Illes Balears, Campus UIB, 07122, Palma de Mallorca, Spain

    Jose L. Rosselló, Sebastià Bota & Jaume Segura

Authors
  1. Jose L. Rosselló
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  2. Sebastià Bota
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  3. Jaume Segura
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Editor information

Editors and Affiliations

  1. Electrical and Computer Engineering Department, University of Patras, Greece

    Vassilis Paliouras

  2. IMEC, Kapeldreef 75, 3001, Heverlee, Belgium

    Johan Vounckx

  3. Dept. of Electrical Engineering, VUB, Brussels, Belgium

    Diederik Verkest

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© 2005 Springer-Verlag Berlin Heidelberg

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Rosselló, J.L., Bota, S., Segura, J. (2005). Compact Static Power Model of Complex CMOS Gates. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_36

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  • DOI: https://doi.org/10.1007/11556930_36

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29013-1

  • Online ISBN: 978-3-540-32080-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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