Abstract
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “u b ”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called variable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate.
In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the u b of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.
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Raja, T., Agrawal, V.D., Bushnell, M. (2005). Design of Variable Input Delay Gates for Low Dynamic Power Circuits. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_45
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DOI: https://doi.org/10.1007/11556930_45
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