Abstract
The energy efficiency of a 0.25 μm general-purpose FIR filter design, based on two-phase clocking, versus a functionally equivalent benchmark, based on one-phase clocking, is demonstrated by means of measurements and transistor level simulations. Architectural improvements enable already a 20% energy savings of the two-phase clocking implementation. Yet, for the first time, the limitations imposed by the supply voltage (< 2.1 V) and the operating frequency (< 10 MHz) on the actual energy efficiency of this low-power strategy are investigated. Transistor level re-design is undertaken: a new slew-insensitive latch is presented and replaced inside the two-phase implementation. Spectre simulations point out the final 30% savings.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Mosch, P., et al.: A 660-μW 50-Mops 1-V DSP for a Hearing Aid Chip Set. IEEE Journal of Solid-State Circuits 35, 1705–1712 (2000)
Arm, C., Masgonty, J., Piguet, C.: Double-Latch Clocking Scheme for Low-Power I.P. Cores. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol. 1918, pp. 217–224. Springer, Heidelberg (2000)
Zyuban, V.: Optimization of Scannable Latches for Low Energy. IEEE Trans. on VLSI 11, 778–788 (2003)
Ching, L., Ling, O.: Low-power and low-voltage D-latch. IEE Electronics Letters 34, 641–642 (1998)
Zyuban, V., Meltzer, D.: Clocking Strategies and Scannable Latches for Low Power Applications. In: ISLPED, pp. 346–351 (2001)
Erdogan, A.T., Zwyssig, E., Arslan, T.: Architectural trade-offs in the design of low power FIR filtering cores. IEE Proc. Circ. Dev. Syst. 151, 10–17 (2004)
Wassner, J., et al.: Waveform Coding for Low-Power Digital Filtering of Speech Data. IEEE Trans. on Signal Processing 51, 1656–1661 (2003)
Nose, K., Sakurai, T.: Analysis and Future Trend of Short-Circuit Power. IEEE Trans. on CAD of IC and Systems 19, 1023–1030 (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Carbognani, F., Bürgin, F., Felber, N., Kaeslin, H., Fichtner, W. (2005). Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_46
Download citation
DOI: https://doi.org/10.1007/11556930_46
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
eBook Packages: Computer ScienceComputer Science (R0)