Abstract
Detailed analysis of CMOS gate behaviour shows that a gate load and input capacitance depends on number of their activated inputs and kind of applied signals i.e. steady state, edge. And in consequence it has an influence on power dissipation. So a reason of the gate switching can be called as the gate driving way. Based on the probability of the gate driving way and associated portion of dissipated energy more accurate model of power dissipation for CMOS gates and circuits is presented. Example of circuits synthesis show power reduction possibilities during design of two-level logic circuits based on information about primary input vector changes – a new circuit activity measure.
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© 2005 Springer-Verlag Berlin Heidelberg
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Brzozowski, I., Kos, A. (2005). Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_47
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DOI: https://doi.org/10.1007/11556930_47
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