Abstract
Contemporary superscalar processors, designed with a one-size-fits-all philosophy, grossly overcommit significant portions of datapath resources that remain unnecessarily activated in the course of program execution. We present a simple scheme for selectively activating regions within the register file and the reorder buffer for reducing leakage as well as dynamic power dissipation. Our techniques result in power savings in excess of 60% in these components, on the average with no performance loss.
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References
Azizi, N., et al.: Low-leakage Asymmetric-cell SRAM. In: Proc, ISLPED 2002, pp. 48–51 (2002)
Goto, M., Sato, T.: Leakage Energy Reduction in Register Renaming. In: Proc. 1st Int’l Workshop on Embedded Computing Systems (ECS) held in conjunction with 24th ICDCS, March 2004, pp. 890–895 (2004)
Heo, S., et al.: Dynamic Fine-grain Leakage Reduction using leakage-biased bitlines. In: Proc. ISCA, pp. 137–147 (2002)
Kim, N.S., et al.: Drowsy Instruction Caches - Leakage Power Reduction using Dynamic Voltage Scaling and Subbank Prediction. In: Proc. MICRO-35, pp. 219–230 (2002)
Mamidipaka, M., Dutt, N.: eCACTI: An Enhanced Power Estimation Model for Onchip Caches, University of California, Irvine, Center for Embedded Computer Systems, TR-04-28 (September 2004)
Narendra, S., et al.: Scaling of Stack Effect and its Application for Leakage Reduction. In: Proc. ISLPED, pp. 195–200 (2001)
Powell, M., et al.: Gated Vdd - A Circuit Technique to Reduce Leakage in Deep Submicron Cache Memories. In: Proc. ISLPED 2000, pp. 90–95 (2000)
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© 2005 Springer-Verlag Berlin Heidelberg
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Khasawneh, S.T., Ghose, K. (2005). An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_51
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DOI: https://doi.org/10.1007/11556930_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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