Abstract
Addition is the most important operation in data processing and its speed has a significant impact on the overall performance of digital circuits. Therefore, many techniques have been proposed for fast adder design. An asynchronous ripple-carry adder is claimed to use a simple circuit implementation to gain a fast average performance as long as the worst cases input patterns rarely happen. However, based on the input vectors from a number of benchmarks, we observe that the worst cases are not exceptional but commonly exist. A simple carry-lookahead scheme is proposed in the paper to speed up the worst-case delay of a ripple-carry adder. The experiment result shows the proposed adder is about 25% faster than an asynchronous ripple-carry adder with only small area and power overheads.
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© 2005 Springer-Verlag Berlin Heidelberg
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Liu, Y., Furber, S. (2005). The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_66
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DOI: https://doi.org/10.1007/11556930_66
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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