Abstract
We present a novel VLSI architecture for division and multiplication in GF(2m), aimed at applications in low cost elliptic curve cryptographic processors. A compact and fast arithmetic unit (AU) was designed which uses substructure sharing between a modified version of the binary extended greatest common divisor (GCD) and the most significant bit first (MSB-first) multiplication algorithms. This AU produces division results at a rate of one per 2m–1 clock cycles and multiplication results at a rate of one per m clock cycles. Analysis shows that the computational delay time of the proposed architecture for division is significantly less than previously proposed bit-serial dividers and has the advantage of reduced chip area requirements. Furthermore, since this novel architecture does not restrict the choice of irreducible polynomials and has the features of regularity and modularity, it provides a high degree of flexibility and scalability with respect to the field size m.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
IEEE 1363, Standard Specifications for Publickey Cryptography (2000)
Menezes, A.: Elliptic Curve Public Key Cryptosystems. Kluwer Academic Publishers, Dordrecht (1993)
Blake, I.F., Seroussi, G., Smart, N.P.: Elliptic Curves in Cryptography. Cambridge University Press, Cambridge (1999)
Wei, S.-W.: VLSI Architectures for Computing exponentiations, Multiplicative Inverses, and Divisions in GF(2m). IEEE Trans. Circuits Syst. II 44(10), 847–855 (1997)
Hasan, M.A., Bhargava, V.K.: Bit-Level Systolic Divider and Multiplier for Finite Fields GF(2m). IEEE Trans. Computers 41(8), 972–980 (1992)
Brunner, H., Curiger, A., Hofstetter, M.: On Computing Multiplicative Inverses in GF(2m). IEEE Trans. Computers 42(8), 1010–1015 (1993)
Guo, J.-H., Wang, C.-L.: Bit-serial Systolic Array Implementation of Euclid’s Algorithm for Inversion and Division in GF(2m). In: Proc. 1997 Int. Symp. VLSI Tech., Systems and Applications, pp. 113–117 (1997)
Kim, C.H., Kwon, S., Kim, J.J., Hong, C.P.: A Compact and Fast Division Architecture for a Finite Field GF(2m). In: Kumar, V., Gavrilova, M.L., Tan, C.J.K., L’Ecuyer, P. (eds.) ICCSA 2003. LNCS, vol. 2667, pp. 855–864. Springer, Heidelberg (2003)
Goodman, J.R.: Energy Scalable Reconfigurable Cryptographic Hardware for Portable Applications. PhD thesis, MIT (2000)
Weste, N., Eshraghian, K.: Principles of CMOS VLSI Design: A System Perspective, 2nd edn. Addison-Wesley, Reading (1993)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kim, C.H., Hong, C.P., Kwon, S. (2005). A Novel Arithmetic Unit over GF(2m) for Low Cost Cryptographic Applications. In: Yang, L.T., Rana, O.F., Di Martino, B., Dongarra, J. (eds) High Performance Computing and Communications. HPCC 2005. Lecture Notes in Computer Science, vol 3726. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11557654_61
Download citation
DOI: https://doi.org/10.1007/11557654_61
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29031-5
Online ISBN: 978-3-540-32079-1
eBook Packages: Computer ScienceComputer Science (R0)