A New Digit-Serial Systolic Mulitplier for High Performance GF(2^m) Applications

Abstract

This paper presents a new digit-serial systolic multiplier over GF(2^m) for cryptographic applications. The proposed array is based on the most significant digit first (MSD-first) multiplication algorithm. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D, where D is the selected digit size. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.