Abstract
Power efficiency is one of the major considerations in the current hardware/software co-designs. This paper models hardware/ software partitioning as an optimization problem with the objective of minimizing power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the idea of solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution in \(O(n.\mathcal{A}.\mathcal{E})\) for n code fragments under the constraints: hardware area \(\mathcal{A}\) and execution time \(\mathcal{E}\). Computational results show that the approximate solution produced by the proposed heuristic algorithm is nearly optimal in comparison to the optimal solution produced by the proposed exact algorithm.
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Wu, J., Srikanthan, T., Yan, C. (2005). Minimizing Power in Hardware/Software Partitioning. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_47
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DOI: https://doi.org/10.1007/11572961_47
Publisher Name: Springer, Berlin, Heidelberg
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