Abstract
This paper presents efficient VLSI architectures for real time processing of separable convolution and lifting based 2-D discrete wavelet transform (DWT). Convolution based architecture uses partitioning algorithm based on the state space representation method and lifting based architecture applies pipelining to each lifting step. Both architectures use recursive pyramid algorithm(RPA) scheduling that intersperses both the row and column operations of the second and following levels among column operations of the first level without using additional filter for row operations of the second and following levels. As a result, proposed architectures have smaller hardware complexity compared to that of other conventional separable architectures with comparable throughput.
This work was supported by the RRC-HECS, CNU under R0202. The support of IDEC CAD tools and equipment in this research is also gratefully acknowledged.
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© 2005 Springer-Verlag Berlin Heidelberg
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Jung, G.C., Park, S.M., Kim, J.H. (2005). Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_65
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DOI: https://doi.org/10.1007/11572961_65
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