Abstract
We propose a novel hardware-based DVS technique called dynamic processor throttling (DPT) for power efficient computations. DPT focuses on the performance balance between the processor and main memory. When a performance imbalance is detected, DPT tries to redress the imbalance by setting the clock frequency and supply voltage of the processor to a well-balanced point.
This paper describes the micro-architecture mechanisms of DPT and shows the evaluation results on energy saving and performance compared with a conventional cache-miss-driven DVS technique. The results reveal that DPT can reduce 17% of the energy with a 3.4% performance degradation and DPT surpasses the conventional technique in both performance and energy.
An erratum to this chapter can be found at http://dx.doi.org/10.1007/11574859_13 .
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Kondo, M., Nakamura, H. (2005). Dynamic Processor Throttling for Power Efficient Computations. In: Falsafi, B., VijayKumar, T.N. (eds) Power-Aware Computer Systems. PACS 2004. Lecture Notes in Computer Science, vol 3471. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11574859_9
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DOI: https://doi.org/10.1007/11574859_9
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