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Formalization of fFSM Model and Its Verification

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Embedded Software and Systems (ICESS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3820))

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Abstract

PeaCE(Ptolemy extension as a Codesign Environment) was developed for the hardware and software codesign framework which allows us to express both data flow and control flow. The fFSM is a model for describing the control flow aspects in PeaCE, but it has difficulties in verifying their specifications due to lack of their formality. Thus we propose the formal semantics of the model based on its execution steps. To verify an fFSM model, it is translated into SMV input language with properties to be checked, automatically. As a result, some important bugs such as race condition, ambiguous transition, and circular transition can be formally detected in the model.

This work was supported in part by IT Leading R&D Support Project funded by Ministry of Information and Communication, Republic of Korea.

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© 2005 Springer-Verlag Berlin Heidelberg

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Park, S., Kwon, G., Ha, S. (2005). Formalization of fFSM Model and Its Verification. In: Yang, L.T., Zhou, X., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds) Embedded Software and Systems. ICESS 2005. Lecture Notes in Computer Science, vol 3820. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599555_35

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  • DOI: https://doi.org/10.1007/11599555_35

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-30881-2

  • Online ISBN: 978-3-540-32297-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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