Abstract
The Interleaved Signature Instruction Stream (ISIS) is a signature embedding technique that allows signatures to co-exist with the main processor instruction stream with a minimal impact on processor performance, without sacrificing error detection coverage or latency.
While ISIS incorporate some novel error detection mechanisms to assess the integrity of the program executed by the main processor, the limited number of bits available in the signature control word question if the detection mechanisms are effective detecting errors in the program execution flow. Increasing the signature size would negatively impact the memory requirements, so this option has been rejected. The effectiveness of such mechanisms is an issue that must be addressed. This paper details those checking mechanisms included within the ISIS technique that are responsible of the assessment of the integrity of the processor execution flow and the experiments carried out to characterize their coverage.
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References
Avresky, D., Grosspietsch, K.E., Johnson, B.W., Lombardi, F.: Embedded fault tolerant systems. IEEE Micro Magazine 18(5), 8–11 (1998)
IEEE Std. 1076-1993: VHDL Language Reference Manual. The Institute of Electrical and Electronics Engineers Inc., New York (1995)
Gunneflo, U., Karlsson, J., Torin, J.: Evaluation of Error Detection Schemes Using Fault Injection by Heavy-ion Radiation. In: Proceedings of the 19th Fault Tolerant Computing Symposium (FTCS 19), Chicago, Illinois, pp. 340–347 (1989)
Czeck, E.W., Siewieorek, D.P.: Effects of Transient Gate-Level Faults on Program Behavior. In: Proceedings of the 20th Fault Tolerant Computing Symposium (FTCS 20), NewCastle Upon Tyne, U.K, pp. 236–243 (1990)
Ohlsson, J., Rimén, M., Gunneflo, U.: A Study of the Effects of Transient Fault Injection into a 32-bit RISC with Built-in Watchdog. In: Proceedings of the 22nd Fault Tolerant Computing Symposium (FTCS 22), Boston, USA, pp. 316–325 (1992)
Siewiorek, D.P.: Niche Sucesses to Ubiquitous Invisibility: Fault-Tolerant Computing Past, Present, and Future. In: Proceedings of the 25th Fault Tolerant Computing Symposium (FTCS 25), Pasadena, USA, pp. 26–33 (1995)
Rodríguez, F., Campelo, J.C., Serrano, J.J.: A Watchdog Processor Architecture with Minimal Performance Overhead. In: Anderson, S., Bologna, S., Felici, M. (eds.) SAFECOMP 2002. LNCS, vol. 2434, pp. 261–272. Springer, Heidelberg (2002)
Rodríguez, F., Campelo, J.C., Serrano, J.J.: The HORUS Processor. In: Proceedings of the XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002), Santander, Spain, pp. 517–522 (2002)
MIPS32 Architecture for Programmers, volume I: Introduction to the MIPS32 Architecture. MIPS Technologies (2001)
AMBA Specification rev2.0. ARM Limited (1999)
Hennessy, J.L., Patterson, D.A.: Computer Architecture. A Quantitative Approach, 2nd edn. Morgan-Kauffmann Publisher, San Francisco (1996)
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Rodríguez, F., Serrano, J.J. (2005). Control Flow Error Checking with ISIS. In: Yang, L.T., Zhou, X., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds) Embedded Software and Systems. ICESS 2005. Lecture Notes in Computer Science, vol 3820. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599555_63
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DOI: https://doi.org/10.1007/11599555_63
Publisher Name: Springer, Berlin, Heidelberg
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