Abstract
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust Constant False Alarm Rate (CFAR) processor with post-detection integration and adaptive censoring (RACPI) is presented in the paper. This detector is effective in conditions of flow from strong impulse interference. The ACPI CFAR processor uses sorting and censoring algorithms. We offer the sorting algorithm to be realized on the basis of the odd-even transposition sort method. We propose the censoring algorithm to be used for obtaining of the noise level estimation and for estimation of the impulse interference parameters. These parameters are needed for automatically choosing the scale factor, which keeps the false alarm rate constant. The real-time implementation of this detection algorithm requires large computational resources because of the great volume and high speed of the incoming data. The time consumption of the sorting and censoring procedures is also very high and therefore the practical realization is difficult. For all these reasons, we choose systolic architectures in the considered case for being more effective than conventional multiprocessor architectures. The computational losses of the systolic architecture are estimated in terms of the number of the processor elements, the computational time and the speed-up needed for real-time implementation.
This work is supported by IIT – 010059/2004, MPS Ltd. Grant “Digital Radar”/2005 and Bulgarian NF “SR” Grant No TH – 1305/2003.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Akimov, P., Evstratov, F., Zaharov, S.: Radio Signal Detection, Moscow. Radio and Communication, 195–203 (1989) (in Russian)
Behar, V., Kabakchiev, C., Dukovska, L.: Adaptive CFAR Processor for Radar Target Detection in Pulse Jamming. VLSI 26(11/12), 383–396 (2000)
Garvanov, I., Behar, V., Kabakchiev, C.: CFAR processors in pulse jamming. In: Dimov, I.T., Lirkov, I., Margenov, S., Zlatev, Z. (eds.) NMA 2002. LNCS, vol. 2542, pp. 291–298. Springer, Heidelberg (2003)
Garvanov, I., Kabakchiev, C.: Sensitivity of API CFAR Detectors Towards Change of Input Parameters of Pulse Jamming. In: Proc. of IRS-2004, Warszawa, Poland, pp. 233–238 (2004)
Garvanov, I., Kabakchiev, C., Daskalov, P.: Systolic architecture of adaptive post detection integration CFAR processor in binomial distribution pulse jamming. In: Lirkov, I., Margenov, S., Waśniewski, J., Yalamov, P. (eds.) LSSC 2003. LNCS, vol. 2907, pp. 448–455. Springer, Heidelberg (2004)
Himonas, S.: CFAR integration processors in randomly arriving impulse interference. IEEE Trans. AES-30(4), 809–817 (1994)
Himonas, S., Barkat, M.: Automatic censored CFAR detection for non-homogeneous environments. IEEE Trans. AES-28(1), 286–304 (1992)
Hwang, J., Jong, J.: Systolic architectures for 2-D ramk order filtering. In: Proc. of ICASAP, September 1990, pp. 90–99 (1990)
Hwang, J., Ritcey, J.: Systolic architectures for radar CFAR detectors. In: Proc. of ICASSP, April 1990, pp. 1025–1028 (1990)
Hwang, J., Ritcey, J.: Systolic architectures for radar CFAR detectors. IEEE Trans. SP-39(10), 2286–2295 (1991)
Lazarov, A., Minchev, C.: Antistealth ISAR Technology for Target Detection and Identification by Linear Frequency Modulated Signal. In: Proc. of 2004 NASA ICNS Conference and Workshop, CD-R (2004)
Lazarov, A., Minchev, C.: Algorithm for automatic determination of ISAR parameters. In: Proc. of 22 DASC Indianapolis, USA, October 2003, CD-R (2004)
Ritcey, J., Hwang, J.: Detection Performance and Systolic Architectures for OSCFAR Detector. In: Proc. of Radar, pp. 112–116 (1990)
Rohling, H.: Radar CFAR Thresholding in Clutter and Multiple Target Situations. IEEE Trans. AES-19(4), 608–621 (1983)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Garvanov, I., Kabakchiev, C., Daskalov, P. (2006). Systolic Architecture for Adaptive Censoring CFAR PI Detector. In: Lirkov, I., Margenov, S., Waśniewski, J. (eds) Large-Scale Scientific Computing. LSSC 2005. Lecture Notes in Computer Science, vol 3743. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11666806_75
Download citation
DOI: https://doi.org/10.1007/11666806_75
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-31994-8
Online ISBN: 978-3-540-31995-5
eBook Packages: Computer ScienceComputer Science (R0)