Abstract
This paper proposes a dual-mapping function for one-way data cache to reduce cache misses, write-back rates, and access time for single-core or multi-core computing processors. Our simulation results show that it reduces cache misses significantly compared to any conventional L1 caches. Simple Scalar simulator has been used for these simulations with SPEC95FP and Minne SPEC2000FP benchmark programs. In addition, it has a simple hardware complexity similar to that of a 2-way SAC (set-associative cache). The proposed cache has good AMAT (average memory access time) compared to a 2-way cache and also uses fewer execution cycles. Simulations over CACTI were performed to evaluate the hardware implications as well.
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Gade, A.S., Chu, Y. (2006). A Case for Dual-Mapping One-Way Caches. In: Grass, W., Sick, B., Waldschmidt, K. (eds) Architecture of Computing Systems - ARCS 2006. ARCS 2006. Lecture Notes in Computer Science, vol 3894. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11682127_10
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DOI: https://doi.org/10.1007/11682127_10
Publisher Name: Springer, Berlin, Heidelberg
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