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International School on Formal Methods for the Design of Computer, Communication and Software Systems

SFM 2006: Formal Methods for Hardware Verification pp 176–210Cite as

Refinement and Theorem Proving

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3965))

Abstract

In this chapter, we describe the ACL2 theorem proving system and show how it can be used to model and verify hardware using refinement.

This is a timely problem, as the ever-increasing complexity of microprocessor designs and the potentially devastating economic consequences of shipping defective products has made functional verification a bottleneck in the microprocessor design cycle, requiring a large amount of time, human effort, and resources [1, 58]. For example, the 1994 Pentium FDIV bug cost Intel $475 million and it is estimated that a similar bug in the current generation Intel Pentium processor would cost Intel $12 billion [2].

This research was funded in part by NSF grants CCF-0429924, IIS-0417413, and CCF-0438871.

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Author information

Authors and Affiliations

  1. College of Computing, Georgia Institute of Technology, Atlanta, GA, 30318, USA

    Panagiotis Manolios

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  1. Panagiotis Manolios
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Editor information

Editors and Affiliations

  1. Istituto di Scienze e Tecnologie dell’Informazione, Università di Urbino “Carlo Bo”, Italy

    Marco Bernardo

  2. FBK-IRST, Povo, Trento, Italy

    Alessandro Cimatti

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Manolios, P. (2006). Refinement and Theorem Proving. In: Bernardo, M., Cimatti, A. (eds) Formal Methods for Hardware Verification. SFM 2006. Lecture Notes in Computer Science, vol 3965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11757283_7

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  • DOI: https://doi.org/10.1007/11757283_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34304-2

  • Online ISBN: 978-3-540-34305-9

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