Abstract
This paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruction scheduling are performed simultaneously at each variable reference where the selection between serialization by scheduling and spilling by register allocation is determined. To make a right selection, the costs of serialization and spilling are estimated with a cost model proposed to reduce the complexity of the estimation. Experiments show that IRIS achieves significant improvements when compared to widely-used existing techniques.
This work was supported by Korea Research Foundation Grant (KRF-2003-003-D00341).
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References
Berson, D.A., Gupta, R., Soffa, M.L.: Integrated instruction scheduling and register allocation techniques. In: Carter, L., Ferrante, J., Sehr, D., Chatterjee, S., Prins, J.F., Li, Z., Yew, P.-C. (eds.) LCPC 1998. LNCS, vol. 1656, pp. 247–262. Springer, Heidelberg (1999)
Briggs, P., Cooper, K.D., Kennedy, K., Torczon, L.: Coloring heuristics for register allocation. In: Proceedings of ACM PLDI 1989, pp. 275–284 (1989)
Fraser, C.W., Hanson, D.R.: A Retargetable C Compiler: Design and Implementation. Benjamin/Cummings (1995)
Gibbons, P.B., Muchnick, S.S.: Efficient instruction scheduling for a pipelined architecture. In: Proceedings of CC 1986, pp. 11–16 (1986)
Goodman, J.R., Hsu, W.C.: Code scheduling and register allocation in large basic blocks. In: Proceedings of Supercomputing 1988, pp. 442–452 (1988)
Kim, D.H., Lee, H.-J.: Fine-Grain Register Allocation based on a Global Spill Costs Analysis. In: Krall, A. (ed.) SCOPES 2003. LNCS, vol. 2826, pp. 255–269. Springer, Heidelberg (2003)
Muchnick, S.S.: Advanced compiler design and implementation. Morgan Kaufmann, SanFrancisco (1997)
Norris, C., Pollock, L.L.: An experimental study of several cooperative register allocation and instruction scheduling strategies. In: Proceedings of MICRO 1995, pp. 169–179 (1995)
Pinter, S.: Register allocation with instruction scheduling: A new approach. In: Proceedings of ACM PLDI 1993, pp. 248–257 (1993)
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Kim, DH., Lee, HJ. (2006). Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors. In: Vassiliadis, S., Wong, S., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2006. Lecture Notes in Computer Science, vol 4017. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11796435_28
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DOI: https://doi.org/10.1007/11796435_28
Publisher Name: Springer, Berlin, Heidelberg
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