Abstract
The effective scheduling of transactions has a great potential for SoC functional verification. Petri nets have proven to be a promising technique for solving scheduling problem. This paper aims at presenting a Petri-net based approach to the scheduling of transactions generated by a test-case generator. Firstly, an extended scheduling timed Petri nets (ESTPN) model is given to support transaction scheduling. Secondly, the short term of ‘scheduling of transactions problem’ is formulated by means of an ESTPN which can accommodate various scheduling policies. Finally, transactions scheduling schemes and scheduling algorithm based on ESTPN are given and cases are studied.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Cadence Berkeley Labs: The Transaction-Based Verification Methodology. Technical Report # CDNL-TR-2000-0825 (August 2000)
Jindal, R., Jain, K.: Verification of Transaction-Level SystemC models using RTL Testbenches. In: Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, pp. 199–204 (2003)
Emek, R., Naveh, Y.: Scheduling of Transactions for System-Level Test-Case Generation. In: Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop, pp. 149–154 (2003)
Emek, R., Jaeger, I., Naveh, Y., Bergman, G., Aloni, G., Katz, Y., Farkash, M., Dozoretz, I., Goldin, A.: X-Gen: A Random Test-Case Generator for Systems and SoCs. In: Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop, pp. 145–150 (2002)
Iyengar, V., Chakrabarty, K., Marinissen, E.J.: Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. In: Proceedings of the 11th Asian Test Symp., pp. 320–325 (2002)
Chou, R., Saluja, K., Agrawal, V.: Scheduling Tests for VLSI Systems under Power Constraints. IEEE Trans. VLSI 5(2), 175–185 (1997)
Rosinger, P., Al-Hashimi, B., Nicolici, N.: Power Profile Manipulation: A New Approach for Reducing Test Application Time under Power Constraints. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 21(10), 1217–1225 (2002)
Zhao, D., Upadhyaya, S.: Adaptive Test Scheduling in SoC’s by Dynamic Partitioning. In: Proceedings of the 17th IEEE Int’l. Symp. Defect and Fault Tolerance in VLSI Systems, pp. 334–342 (2002)
Zhao, D., Upadhyaya, S.: Power Constrained Test Scheduling with Dynamically Varied TAM. In: Proceedings of the 21st VLSI Test Symp., pp. 273–278 (2003)
Coffman Jr., E.G., Garey, M.R., Johnson, D.S., Tarjan, R.E.: Performance Bounds for Level-Oriented Two-Dimensional Packing Algorithm. SIAM J. Computing 9, 809–826 (1980)
Huang, Y., Cheng, W.-T., Tsai, C.-C., Mukherjee, N., Samman, O., Zaidan, Y., Reddy, S.M.: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC Design. In: Proceedings of IEEE Asian Test Symposium (ATS), pp. 265–270 (2001)
Huang, Y., Cheng, W.-T., Tsai, C.-C., Mukherjee, N., Samman, O., Zaidan, Y., Reddy, S.M.: On Concurrent Test of Core-Based SoC Design. J. Electronic Testing: Theory and Applications 18, 401–414 (2002)
Iyengar, V., Chakrabarty, K., Marinissen, E.J.: Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs. In: Proc. 39th Design Automation Conf., pp. 685–690 (2002)
Huang, Y., Reddy, S.M., Cheng, W.-T., Reuter, P., Mukherjee, N., Tsai, C.-C., Samman, O., Zaidan, Y.: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3D Bin Packing Algorithm. In: Proceedings of ITC 2002, pp. 74–82 (2002)
Huang, Y., Cheng, W.-T., Tsai, C.-C., Mukherjee, N., Reddy, S.M.: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. In: Proceedings of the Fourth International Symposium on Quality Electronic Design, pp. 99–104 (2003)
Nourani, M., Papachristou, C.: An ILP Formulation to Optimize Test Access Mechanism in SoC Testing. In: Proceedings of ITC 2000, pp. 902–910 (2000)
Chakrabarty, K.: Test Scheduling for Core-Based Systems Using Mixed Integer Linear Programming. IEEE Trans. Computer-Aided Design 19, 1163–1174 (2000)
Iyengar, V., Chakrabarty, K.: Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. In: Proceedings of the 19th IEEE VLSI Test Symposium, pp. 368–374 (2001)
Nourani, M., Chin, J.: Power-Time Trade-Off in Test Scheduling for SoCs. In: Proceedings of IEEE International Conference on Computer Design (ICCD 2003), pp. 548–553 (2003)
Chin, J., Nourani, M.: FITS: An Integrated ILP-Based Test Scheduling Environment. IEEE Trans. on computer 54(12), 1598–1613 (2005)
van der Aalst, W.M.P.: Petri net based scheduling. Computing Science Reports 95/23, Eindhoven University of Technology, Eindhoven (1995)
Tsai, J.J.P., Yang, S.J., Chang, Y.-H.: Timing Constraints Petri Net and Their Application to Schedulability Analysis for Real-Time System Specification. IEEE Transaction on Software Engineering 21(1) (1995)
Huifang, L., Yushun, F.: Schedulability analysis method for Timing Constraint Petri Nets. Tsinghua Science and Technology 7(6), 596–601 (2002)
Roux, O.H., Deplanche, A.M.: A t-time Petri net extension for real time-task scheduling modeling. European Journal of Automation (JESA) 36, 973–987 (2002)
Lime, D., Gardey, G., Magnin, M., Roux, O(H.): Romeo: A Tool for Analyzing Time Petri Nets. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 418–423. Springer, Heidelberg (2005)
Berthomieu, B., Ribet, P.-O., Vernadat, F.: The tool TINA: Construction of abstract state. spaces for Petri nets and time Petri nets. International Journal of Production Research 42(14) (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yu, J., Li, T., Guo, Y., Tan, Q. (2006). Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation. In: Sha, E., Han, SK., Xu, CZ., Kim, MH., Yang, L.T., Xiao, B. (eds) Embedded and Ubiquitous Computing. EUC 2006. Lecture Notes in Computer Science, vol 4096. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802167_74
Download citation
DOI: https://doi.org/10.1007/11802167_74
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36679-9
Online ISBN: 978-3-540-36681-2
eBook Packages: Computer ScienceComputer Science (R0)