Abstract
In this paper, we present a new kind of reconfigurable soft core processor based on the concept of Explicitly Parallel Instruction Computing (EPIC). The implementation targets a dynamic System-on-a-Chip utilizing Field Programmable Gate Arrays. In contrast to established EPIC cores, the number of functional units is adjusted at run-time and depends only on the available resources of the FPGA. Thus, our EPIC core dynamically trades space versus processing performance. Since we employ only standard functional units, we can use off-the-shelf EPIC compilers for efficient code generation.
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© 2006 Springer-Verlag Berlin Heidelberg
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Scholz, R., Buchenrieder, K. (2006). Self Reconfiguring EPIC Soft Core Processors. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_25
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DOI: https://doi.org/10.1007/11802839_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
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