Abstract
A previously proposed Reconfigurable Instruction Set Processor (RISP) architecture, which tightly couples a coarse-grain Reconfigurable Functional Unit (RFU) to a RISC processor, is considered. Two architectural enhancements, namely partial predicated execution and virtual opcode are presented. An automated development framework for the introduced architecture is proposed. In order to evaluate both the architecture and the development framework a complete MPEG-2 encoder application is used. The efficiency of the predicated execution is proved and impressive speedup of the application is produced. Also, the use of virtual opcode to alleviate the opcode space explosion is demonstrated.
This work was supported by PENED 2003 programme of the General Secretariat for Research and Technology of Greece and the European Union.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
DeHon, A., Wawrzynek, J.: Reconfigurable Computing: What, Why, and Implications for Design Automation. In: DAC 1999, pp. 610–615 (1999)
Vassiliadis, N., Kavvadias, N., Theodoridis, G., Nikolaidis, S.: A RISC Architecture Extended by an Efficient Tightly Coupled Reconfigurable Unit. In: ARC 2005, pp. 41–49 (2005)
Mahlke, S., Hank, R., McCormick, J., August, D., Hwu, D.: A comparison of full and partial predicated execution support for ILP processors. In: ISCA 1995, pp. 138–150 (1995)
Callahan, T.J., Hauser, J.R., Wawrzynek, J.: The Garp Architecture and C Compiler. IEEE Computer 33(4), 62–69 (2000)
Gokhale, M.B., Stone, J.M.: NAPA C: Compiling for a Hybrid RISC/FPGA Architecture. In: FCCM 1998, p. 126 (1998)
Vassiliadis, S., Wong, S., Gaydadjiev, G., Bertels, K., Kuzmanov, G., Moscu Panainte, E.: The MOLEN Polymorphic Processor. IEEE Trans. on Computers 53(11), 1363–1375 (2004)
Miyamori, T., Olukotun, K.: REMARC: Reconfigurable Multimedia Array Co-Processor. IEICE Trans. Information Systems E82-D(2), 389–397 (1999)
Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R., Laufer, R.: Piperench: A Coprocessor for Streaming Multimedia Acceleration. In: ISCA 1999, pp. 28–39 (1999)
Razdan, R., Smith, M.D.: A High-Performance Microarchitecture with Hardware-Programmable Functional Units. MICRO 27, 172–180 (1994)
Ye, Z.A., Shenoy, N., Baneijee, P.: A C compiler for a Processor with a Reconfigurable Functional Unit. In: FPGA 2000, pp. 95–100 (2000)
La Rosa, A., Lavagno, L., Passerone, C.: Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems. IEEE Design and Test of Computers 22(1), 28–38 (2005)
Machine-SUIF research compiler, See website: http://www.eecs.harvard.edu/hube/research/machsuif.html
Kavvadias, N., Nikolaidis, S.: Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding. In: ASAP 2005, pp. 140–145 (2005)
Alippi, C., Fornaciari, W., Pozzi, L., Sami, M.: A DAG Based Design Approach for Reconfigurable VLIW Processors. In: DATE 1999, pp. 778–779 (1999)
Optimization Passes for Machine Suif, See website: http://lapwww.epfl.ch/dev/machsuif/opt_passes/
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In: MICRO, pp. 330–335 (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Vassiliadis, N., Theodoridis, G., Nikolaidis, S. (2006). Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_30
Download citation
DOI: https://doi.org/10.1007/11802839_30
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
Online ISBN: 978-3-540-36863-2
eBook Packages: Computer ScienceComputer Science (R0)