Abstract
Repeater insertion is one of the most effective techniques to reduce the propagation delay related to long interconnects.
However, its application to deep submicron technologies leads to sub-optimal results if the traditional sizing rules are followed.
In the paper the Authors show the behaviour of deep-sub micron devices may differ significantly from the conventional one due to transistor parasitic capacitance. As a consequence, well-exploited assumption as linear relationship between channel width and output conductance of the CMOS gate start to fails, as well as it does optimisation techniques based upon them. A developed formula for buffer sizing is proposed based on a simplified model allowing MOS parasitic to be taken into account. Up to 50% area and leakage power saving can be obtained.
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© 2006 Springer-Verlag Berlin Heidelberg
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Pugliese, A., Cappuccino, G., Cocorullo, G. (2006). A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_30
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DOI: https://doi.org/10.1007/11847083_30
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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