Abstract
The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a progressive refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the progressive refinement of hierarchical designs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Adya, S.N., et al.: Benchmarking for large-scale placement and beyond. In: Proceedings of the 2003 international symposium on Physical design, pp. 95–103. ACM Press, New York (2003)
Xiu, Z., Papa, D.A., Chong, P., Albrecht, C., Kuehlmann, A., Rutenbar, R.A., Markov, I.L.: Early research experience with openaccess gear: an open source development environment for physical design. In: ISPD 2005: Proceedings of the 2005 international symposium on physical design, pp. 94–100. ACM Press, New York (2005)
Alexandre, C., Clement, H., Chaput, J.P., Sroka, M., Masson, C., Escassut, R.: Tsunami: An integrated timing-driven place and route research platform. In: DATE 2005: Proceedings of the conference on Design, Automation and Test in Europe, pp. 920–921. IEEE Computer Society, Los Alamitos (2005)
Abou-Seido, A.I., Nowak, B., Chu, C.: Fitted elmore delay: a simple and accurate interconnect delay model. IEEE Trans. Very Large Scale Integr. Syst. 12(7), 691–696 (2004)
Kong, T.T.: A novel net weighting algorithm for timing-driven placement. In: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 172–176. ACM Press, New York (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Alexandre, C., Sroka, M., Clément, H., Masson, C. (2006). Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_31
Download citation
DOI: https://doi.org/10.1007/11847083_31
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
eBook Packages: Computer ScienceComputer Science (R0)