Abstract
Crosstalk analysis has become a significant part of the design cycle of high performance processors in nanometer technologies. In this paper we demonstrate that current crosstalk analysis techniques that ignore the degrading effect of multiple crosstalk events on receiver noise rejection curve filter significant number of true violations. We also demonstrate that techniques that take into account the multiple crosstalk events with traditional receiver modeling result in large number of false violations. We propose improved crosstalk analysis techniques that are multiple noise event aware (MNEA) with minimal changes to existing crosstalk analysis. We also propose enhancements to existing receiver models so they can be used with the MNEA analysis resulting in reduction of number of false violations by 68%-98% while guaranteeing identification of all true violations.
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References
Caignet, F., Delmas-Bendhia, S., Sicard, E.: The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology. Proceedings IEEE 89 (2001)
Heydari, P., Pedram, M.: Capacitive Coupling Noise in High-Speed VLSI Circuits. Transactions IEEE CAD 24 (2005)
Shepard, K.L.: Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits. Transactions IEEE CAD 18 (1999)
Levy, R., et al.: ClariNet: A noise analysis tool for deep submicron design. In: DAC (2000)
Odabasioglu, A., Celik, M., Pileggi, L.T.: PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm. Transactions IEEE CAD 17 (1998)
Devgan, A.: Efficient Coupled Noise Estimation for On-Chip Interconnects. In: Proceedings IEEE/ACM CAD International Conference (1997)
Krauter, B., Widiger, D.: Variable Frequency Crosstalk Noise Analysis: A Methodology to Guarantee Functionality from dc to fmax. In: Proceedings DAC (2000)
Tutuianu, B., Baldick, R., Johnstone, M.: Nonlinear Driver Models for Timing and Noise Analysis. Transactions IEEE CAD 23 (2004)
Bai, X., Chandra, R., Dey, S., Srinivas, P.V.: Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits. Transactions IEEE CAD 23 (2004)
Chen, W., Gupta, S.K., Breuer, M.: Analytic Models for Crosstalk Excitation and Propagation in VLSI Circuits. Transactions IEEE CAD 21 (2002)
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© 2006 Springer-Verlag Berlin Heidelberg
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Nanua, M., Blaauw, D. (2006). Receiver Modeling for Static Functional Crosstalk Analysis. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_32
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DOI: https://doi.org/10.1007/11847083_32
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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