Abstract
By using output control and MTCMOS techniques, we propose two low power low clock swing D flip-flops. Experimental results show that the leakage power of the proposed flip flops can be reduced more than an average of 59% in standby mode and in active mode the total power consumption can be reduced more than an average of 53% while the delay time stays the same. It is also show that the proposed D flip-flops can work even when the clock swing is nearly as low as V dd /3, though the delay time is much increased.
This work was sponsored in party by NSFC under grant #90207001.
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© 2006 Springer-Verlag Berlin Heidelberg
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Lin, S., Gao, H., Yang, H. (2006). Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_47
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DOI: https://doi.org/10.1007/11847083_47
Publisher Name: Springer, Berlin, Heidelberg
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