Abstract
The nested Miller frequency compensation (NMC) for multistage amplifiers is a well-known technique used to overcome the phase margin degradation due the low-frequency poles introduced by cascading stages. The NMC exploits both the Miller capacitance-multiplier effect and the pole-splitting action. In literature NMC capacitor sizing rules have been presented to design amplifiers characterised by a third-order Butterworth unity-gain closed-loop response. In the paper, the Authors show these criteria neglecting transistor parasitic capacitances, may lead to incorrect amplifier behaviour when small load capacitances have to be driven. A developed model, allowing better pole location estimation, is also presented.
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© 2006 Springer-Verlag Berlin Heidelberg
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Pugliese, A., Cappuccino, G., Cocorullo, G. (2006). Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_51
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DOI: https://doi.org/10.1007/11847083_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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