Abstract
In this paper, a method is proposed to analyze the minimum average cycle period of the timed circuits. Timed Petri net is used to model timed circuits. Our method is focus on structural analysis of the Petri net model of the timed circuits, which is another way to reduce the state space of the analyzed model. Then an algorithm is proposed to optimize the performance of timed circuit by asynchronous retiming technique. The algorithm balances the asynchronous pipelines to gain the target cycle period while minimize the area at the same time. Experimental results demonstrate the computational feasibility and effectiveness of both approaches.
This work has been supported by the National Natural Science Foundation of China (Grant 90407022).
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References
Myers, C.J., Meng, T.H.-Y.: Synthesis of timed asynchronous circuits. IEEE Transactions on Very Large Scale Integration (VLSI) systems 1(2), 106–119 (1993)
Sutherland, I.E.: Micropipelines. Communications of the ACM 32(6), 720–738 (1989)
Nowick, S.M., Yun, K.Y., Dill, D.L.: Practical asynchronous controller design. In: Proc. International Conf. Computer Design (ICCD), pp. 341–345. IEEE Computer Society Press, Los Alamitos (1992)
Leiserson, C., Saxe, J.: Optimizing synchronous systems. Journal of VLSI and Computer Systems 1(1), 41–67 (1983)
Murata, T.: Petrinet: properties, analysis and applications. Proceedings of the IEEE 77(4), 541–579 (1989)
Yaw, Y., Wei, B.W.Y., Ramamoorthy, C.V., et al.: Extension on Performance Evaluation Techniques for Concurrent Systems. In: Proceedings of Twelfth International Computer Software and Applications Conference, COMPSAC 1988, October 5-7, pp. 480–484 (1988)
Lawler, E.L.: Combinatorial Optimization: Networks and Matroids. Holt, Reinhart, and Winston, New York, NY, USA (1976)
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© 2006 Springer-Verlag Berlin Heidelberg
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Wang, L., Wang, Zy., Dai, K. (2006). Cycle Period Analysis and Optimization of Timed Circuits. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_50
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DOI: https://doi.org/10.1007/11859802_50
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40056-1
Online ISBN: 978-3-540-40058-5
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