Abstract
An area-efficient pulse mode hardware neuron model with sigmoid-like activation function for artificial neural networks implementations is presented. The neuron activation function is based on an enhanced version of the voting circuit previously reported in the literature. The proposed model employs pulse stream computations and statistical saturation to deal with the nonlinearities inherent to neural computations. This approach provides an embedded hardware implementation feasibility favoring silicon area efficiency rather than speed. Implementation results on Field Programmable Gate Array (FPGA) technology shows the proposed neuron model requires fewer hardware resources than previous implementations and it is especially attractive for neurons with wide receptive fields in large neural networks. Experimental results are presented to highlight the improvements of the proposed model.
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© 2006 Springer-Verlag Berlin Heidelberg
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Torres-Huitzil, C. (2006). A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks. In: King, I., Wang, J., Chan, LW., Wang, D. (eds) Neural Information Processing. ICONIP 2006. Lecture Notes in Computer Science, vol 4234. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11893295_127
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DOI: https://doi.org/10.1007/11893295_127
Publisher Name: Springer, Berlin, Heidelberg
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