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Time Aware Modelling and Analysis of Multiclocked VLSI Systems

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Formal Methods and Software Engineering (ICFEM 2006)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 4260))

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Abstract

We introduce a formal, time aware framework for modelling and analysis multiclocked VLSI systems. We define a delay calculus framework for our timed formalism, and, furthermore, constraints with which to confine the correctness of the system under development, not only logically but also with respect to timing characteristics. We give an elaborate definition of the timed formalism, Timed Action Systems, and its delay models. With the timing aware formal development framework it is possible to obtain information of multiclocked VLSI systems already at high abstraction levels as our application, a GALS (globally asynchronous, locally synchronous) system, shows.

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Westerlund, T., Plosila, J. (2006). Time Aware Modelling and Analysis of Multiclocked VLSI Systems. In: Liu, Z., He, J. (eds) Formal Methods and Software Engineering. ICFEM 2006. Lecture Notes in Computer Science, vol 4260. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11901433_40

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  • DOI: https://doi.org/10.1007/11901433_40

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-47460-9

  • Online ISBN: 978-3-540-47462-3

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