Abstract
We introduce a formal, time aware framework for modelling and analysis multiclocked VLSI systems. We define a delay calculus framework for our timed formalism, and, furthermore, constraints with which to confine the correctness of the system under development, not only logically but also with respect to timing characteristics. We give an elaborate definition of the timed formalism, Timed Action Systems, and its delay models. With the timing aware formal development framework it is possible to obtain information of multiclocked VLSI systems already at high abstraction levels as our application, a GALS (globally asynchronous, locally synchronous) system, shows.
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References
Allen, J.F.: Maintaining knowledge about temporal intervals. Commun. ACM 26(11), 832–843 (1983)
Alur, R., Dill, D.L.: A theory of timed automata. Theoretical Computer Science 126(2), 183–235 (1994)
Back, R.-J., Sere, K.: From modular systems to action systems. In: Proc. of Formal Methods Europe 1994, Spain. LNCS. Springer, Heidelberg (1994)
Berry, G., Gonthier, G.: The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming 19(2), 87–152 (1992)
Berry, G., Sentovich, E.: Multiclock Esterel. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 110–125. Springer, Heidelberg (2001)
Bormann, D.S., Cheung, P.Y.: Asynchronous wrapper for heterogeneous systems. In: Computer Design: VLSI in Computers and Processors, pp. 307–314 (1997)
Chapiro, D.M.: Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Standford University (1984)
Dijkstra, E.W.: A Discipline of Programming. Prentice-Hall International, Englewood Cliffs (1976)
Dobkin, R., Ginosar, R., Sotiriou, C.: Data synchronisation issues in gals socs. In: International Conference on Asynchronous Circuits and Systems, pp. 170–179 (2004)
Guernic, P.L., Gautier, T., Borgne, M.L., Maire, C.L.: Programming real-time applications with SIGNAL. Proceedings of the IEEE 79(9), 1321–1335 (1991)
Halbwachs, N., Caspi, P., Raymond, P., Pilaud, D.: The synchronous data-flow programming language LUSTRE. Proceedings of the IEEE 79(9), 1305–1320 (1991)
He, J., Turner, K.J.: Specifying hardware timing with ET-LOTOS. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 161–166. Springer, Heidelberg (2001)
Kim, H., Beerel, P.A., Stevens, K.: Relative timing based verification of timed circuits and systems. In: Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems, pp. 115–124 (April 2002)
Krstic, M., Grass, E., Stahl, C.: Request-driven gals technique for wireless communication system. In: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp. 76–85. IEEE, Los Alamitos (2005)
Mekie, J., Chakraborty, S., Venkatarami, G., Thiagarajan, P., Sharma, D.: Interface design for rationally clocked gals systems. In: Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems, pp. 160–171. IEEE, Los Alamitos (2006)
Muttersbach, J., Villiger, T., Fichtner, W.: Practical design of globally-asynchronous locally-synchronous systems. In: Advanced Research in Asynchronous Circuits and Systems, pp. 52–59 (2000)
Negulescu, R., Peeters, A.: Verification of speed-dependences in single-rail handshake circuits. In: Advanced Research in Asynchronous Circuits and Systems, pp. 159–170 (1998)
Plosila, J.: Self-Timed Circuit Design - The Action System Approach. PhD thesis, University of Turku (1999)
Plosila, J., Liljeberg, P., Isoaho, J.: Modelling and refinement of an on-chip communication architecture. In: Lau, K.-K., Banach, R. (eds.) ICFEM 2005. LNCS, vol. 3785, pp. 219–234. Springer, Heidelberg (2005)
Rajan, B., Shyamasundar, R.: Multiclock Esterel: a reactive framework for asynchronous design. In: Parallel and Distributed Processing Symposium, pp. 201–209 (2000)
Sekerinski, E., Sere, K.: A theory of prioritizing composition. The Computer Journal 39(8), 701–712 (1996)
Stevens, K., Ginosar, R., Rotem, S.: Relative timing. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 129–140 (February 2003)
Turner, K.J., Sinnott, R.O.: DILL: Specifying digital logic in LOTOS. In: Proc. Formal Description Techniques VI, pp. 71–86. North-Holland, Amsterdam (1994)
Westerlund, T., Plosila, J.: Formal timing model for hardware components. In: Proceedings of the 22nd NORCHIP Conference, Norway, pp. 293–296 (November 2004)
Westerlund, T., Plosila, J.: Back-annotation of timing information into a formal hardware model: A case study. In: International Symposium on Signals, Circuits, and Systems - ISSCS 2005, Romania, pp. 625–628 (July 2005)
Westerlund, T., Plosila, J.: Formal modelling of synchronous hardware components for system-on-chip. In: International Symposium on System-On-Chip, Finland, pp. 116–119 (November 2005)
Westerlund, T., Plosila, J.: Time aware system refinement. In: REFINE 2006 Workshop (2006) (page to appear)
Zhuang, S., Carlsson, J., Wanhammar, L.: A design approach for gals based systems-on-chip. In: Solid-State and Integrated Circuits Technology, pp. 1368–1371 (2004)
Zhuang, S., Carlsson, J., Wanhammar, L.: A design approach for gals based systems-on-chip. In: 7th Internation Conference on Solid-State and Integrated Circuits Technology, vol. 2, pp. 1368–1371 (October 2004)
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Westerlund, T., Plosila, J. (2006). Time Aware Modelling and Analysis of Multiclocked VLSI Systems. In: Liu, Z., He, J. (eds) Formal Methods and Software Engineering. ICFEM 2006. Lecture Notes in Computer Science, vol 4260. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11901433_40
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DOI: https://doi.org/10.1007/11901433_40
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