The Design of Random Number Generator in an Embedded Crypto Module

Abstract

When using a real random number generator (RNG) with only a hardware component, as required for statistical randomness, it is difficult to create an unbiased and stable random bit stream. Although the hardware generating processor generates an output bit stream quickly, if the software filter algorithm is not efficient, the RNG consumes a relatively large amount of time. This factor becomes the limiting condition when the RNG is applied. Accordingly, this paper proposes a model approach to ensure the model of software filtering in the RNG processor and the chaos function model in the crypto module. Therefore, in the embedded crypto processor, the mixed model guarantees randomness of the output stream, is generated from the combined chaos function with a tent map transformation and a hardware random number generation component in sensor crypto communication.