Abstract
With the development of semiconductor technology, multicore is integrated on one chip [1]. In CMP, more than one core accessing the shared data will cause memory access conflict and the problem of cache coherence. Cache coherence is a precondition for the system to function correctly. So it is a key problem in CMP. In this paper, we propose a new pseudo sharing level one data cache in a chip multiprocessor architecture (PSDMP). In PSDMP, the request of memory access will be propagated on a ring chain. This method can reduce both the complexity of the design and the load of L2 cache. Simulation results show that performance of PSDMP improves about 30% averagely than another CMP which uses MESI protocol, especially the best is about 100% for the parallel applications which has many inter-processor communications for modifying shared data. In one word, PSDMP is promising processor architecture.
This work is supported by National Natural Science Foundation of China(60473079).
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References
Zhimin, T.: Prospect of tera-scale microprocessors. Information Technology Letters 8 (2004)
Li, F., Ji-lu, C., Zhen-bo, Z.: Establishment of LC memory model and Cache consistency protocol. Journal of North China Electric Power University (October 2002)
Viswanath, V.: Multi-log Processor Towards Scalable Event Driven Multiprocessors. In: DSD 2004 (2004)
Suh, T.: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems. In: DATE 2004 (2004)
Sorin, D.J.: Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Transactions on Parallel and Distributed Systems 13(6) (June 2002)
Gao, G.R., Sarkar, V.: Location Consistency-A New Memory Model and Cache Consistency Protocol. IEEE Transactions on Computers 49(8) (August 2000)
Jiang-Hua, W., Shu-Ming, C.: MOSI: a SMT Microarchitecture Based On VLIW Processors. Chinese Journal of Computer 39 (2006)
Shuming, C., Zhentao, L.: Research and Development of High Performance YHFT Digital Signal Processor. Journal of Computer Research and Development 43 (2006)
Pengyong, M., Shuming, C., Guokuan, L.: The Design of Cache Controller Supporting Two Parallel Cache Accesses. High Technology Letters (2002)
Dan-Yu, Z., Peng-Yong, M.A., Shu-Ming, C.: The Mechanism of Miss Pipeline Cache Controller based on Two Class VLIW Architecture. Journal of Computer Research and Development (2005)
Guang-Qi, H., Zi-Mu, L., Xing-Ming, Z., Yong, D.: Shared Multi Ported Data Cache Architecture: SMPDCA. Chinese Journal of Computer (December 2001)
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© 2006 Springer-Verlag Berlin Heidelberg
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Ma, P., Hu, X., Chen, S., Guo, Y. (2006). Pseudo Share Data Cache in Multiprocessor: PSDMP. In: Min, G., Di Martino, B., Yang, L.T., Guo, M., Rünger, G. (eds) Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. ISPA 2006. Lecture Notes in Computer Science, vol 4331. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11942634_6
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DOI: https://doi.org/10.1007/11942634_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-49860-5
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