Software Challenges for Multicore Computing

Abstract

Current technological trends have led chip manufacturers to move to designs that include multiple processors, or cores, on each chip. In some cases, these processors are homogeneous (e.g., Intel, AMD) and in others they are heterogeneous (e.g., Cell). It is clear is that these designs represent the future of computational chips and they will effect enormous changes in the way software is designed and implemented to take advantage of their power. In this talk, I will survey issues that will be critical to making systems, particularly HPC systems based on multicore chips usable by application developers. The talk presents a series of “big questions” (not to be confused with “grand challenges”) about software, particularly compilers and programming tools, for multicore chips. Topics include utilization of bandwidth (both on and off chip), on-chip memory hierarchy (shared versus separate caches), methods for exploitation of parallelism (data parallelism versus pipelining), and inter-core synchronization mechanisms. The talk will also address the special challenges presented by on-chip heterogeneous parallelism such as that found on the IBM Cell chip and planned for future Intel designs. I will conclude with a discussion of my own group’s preliminary research on compilers and tools for systems based on multicore chips and future research directions for the computer science community as a whole.