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Pacific-Rim Symposium on Image and Video Technology

PSIVT 2006: Advances in Image and Video Technology pp 861–868Cite as

Fractional Full-Search Motion Estimation VLSI Architecture for H.264/AVC

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Part of the book series: Lecture Notes in Computer Science ((LNIP,volume 4319))

Abstract

A novel half-pel full-search motion estimation VLSI architecture for H.264/AVC video encoders is presented in this paper. Based on the processing element arrays eliminating redundant data accesses and attaining 100 % utilization, the architecture can be implemented with low clock rate while having high processing throughput. Such an implementation is particularly suited to applications requiring real time operations with high compression efficiency and low power.

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References

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Author information

Authors and Affiliations

  1. Department of Electronics Engineering, Ching-Yun University, Chungli, 320, Taiwan

    Chien-Min Ou

  2. Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan

    Huang-Chun Roan & Wen-Jyi Hwang

Authors
  1. Chien-Min Ou
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  2. Huang-Chun Roan
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  3. Wen-Jyi Hwang
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Editor information

Editors and Affiliations

  1. Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan

    Long-Wen Chang

  2. Department of Electrical Engineering, National Chung Cheng University, 621, Chia-Yi, Taiwan, ROC

    Wen-Nung Lie

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© 2006 Springer-Verlag Berlin Heidelberg

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Cite this paper

Ou, CM., Roan, HC., Hwang, WJ. (2006). Fractional Full-Search Motion Estimation VLSI Architecture for H.264/AVC. In: Chang, LW., Lie, WN. (eds) Advances in Image and Video Technology. PSIVT 2006. Lecture Notes in Computer Science, vol 4319. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11949534_86

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  • DOI: https://doi.org/10.1007/11949534_86

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-68297-4

  • Online ISBN: 978-3-540-68298-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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