Abstract
In this paper, we discussed several problems in the design of hardware algorithms and logic design automation. The theory of complexty of logic circuits and parallel computation will form the foundation of design of hardware algorithms which will become more important for larger VLSI systems. Especially, the relation between the complexities of software and hardware is very important for practical system design, because systems are combination of software and hardware.
Design automation is one of the most highlighted fields in computer science. There are still many hard problems to solve in developing much efficient design automation system. Researches on high-level hardware design languages, automatic logic design from descriptions of three languages and design verification techniques for large systems have been increasing. Several techniques developed in the software engineering will be applied to these area.
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"Highly Parallel Computing" Edited by L.S.Hayens, IEEE Computer, vol.15, no.1, pp. 7–96, Jan. 1982.
S.Yajima, H.Yasuura and Y.Kambayashi, "Design of Hardware Algorithms and Related Problems", IECE Technical Rep. AL81-86, Dec. 1981 (in Japanese).
N. Tokura, "VLSI Algorithms and Area-Time Complexity", Joho-Shori vol.23, no.3, pp.176–186, March 1982 (in Japanese)
C.A. Mead and L.A. Conway, "Introduction to VLSI Systems", Addison-Wesley, Reading, Mass., 1980.
H.T.Kung, "The Structure of Parallel Algorithms", Advanced in Computers, vol.19, Academic Press, 1980.
M.Foster and H.T.Kung, "The Design of Special-Purpose VLSI Chips", IEEE Computer, vol.13, no.1, Jan. 1980.
C.D.Thompson, "Area-Time Complexity for VLSI", Proc. 11th Symposium on the Theory of Computing, pp.81–88, May 1979.
R.P. Brent and H.T. Kung, "The Area-Time Complexity of Binary Multiplication", JACM, vol.28, no.3, pp.521–534, July 1981.
J.P.Gray, "Introduction to Silicon Compilation", Proc. 16th DA Conference, pp.305–306, June 1979.
K. Hwang, "Computer Arithmetic:Principle, Architecture and Design", John-Wiley & Sons, Reading, Mass., 1979.
L.B.Jackson, S.F.Kaiser and H.S.McDonald, "An Approach to the Implementation of Digital Filters," IEEE Trans. Audio Electro., AU-16, Sept. 1968.
W.J. Stenzel, W.J. Kubitz and G.H. Garcia, "A Compact High-Speed Parallel Multiplication Scheme," IEEE Trans. on Comput, vol.C-26, no.10, pp.948–957, Oct. 1977.
A.Karatsuba and Y.Ofman, "Multiplication of Multidigit Numbers with Computers", Dokl. Akad. Nauk. SSSR, no.145, Feb. 1962.
C.S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Trans. on Electro. Comput., vol EC-13, no.1, pp.14–17, Feb. 1964.
A.V. Aho, J.E. Hopcroft and J.D. Ullman, "Design and Analysis of Computer Algorithms", Addison-Wesley, Reading, Mass., 1974.
D.E. Muller and F.P. Preparata, "Bounds to Complexities of Networks for Sorting and Switching", JACM, vol.22, no.2, pp.195–201, Apr. 1975.
C.D. Thompson and H.T. Kung, "Sorting on a Mesh-Connected Parallel Computer", CACM, vol.20, no.4, Apr.1977.
D.Nassimi and S.Sahni, "Bitonic Sort on a Mesh-Connected Parallel Computer", IEEE Trans. Comput., vol.C-28, no.1, Jan. 1979.
M.Maekawa, "Parallel Sort and Join for High Speed Database Machine Operations", AFIPS Conf. Proc., vol.50, June 1981.
L.E.Winslow and Y.C.Chow, "Parallel Sorting Machines:Their Speed and Efficiency", AFIPS Conf. Proc., vol.50, June 1981.
T.C.Chen, V.Y.Lum and C.Tung, "The Rebound Sorter:An Efficient Sort Engine for Large Files", Proc. 4th VLDB, pp.312–318, Sept. 1978.
H. Yasuura and N. Takagi, "A High-Speed Sorting Circuit Using Parallel Enumeration Sort", Trans. IECE, vol.J65-D, no.2, pp.179–186, Feb.1982 (in Japanese).
S.Todd, "Algorithm and Hardware for a Merge Sort Using Multiple Processors", IBM Journal of R. & D., vol.22, no.5, Sept. 1978.
Y.Tanaka, Y.Nozawa and A.Masuyama, "Pipeline Searching and Sorting Modules as Components of a Data Flow Database Computer", Proc. IFIP80, pp.427–432, Oct. 1980.
H.Yasuura, "Hardware Algorithms for VLSI", Proc. Joint Conf. of 4 Institutes Related on Electric Engineering, 34-4, Oct. 1981 (in Japanese).
J.E. Savage, "The Complexity of Computing", Wiley-Interscience, Reading, Mass., 1976.
S.H. Unger, "Tree Realizations of Iterative Circuits", IEEE Trans. Comput., vol.c-26, no.4, pp.365–383, Apr. 1977.
H.Yasuura, Y.Ooi and S.Yajima, "On Macroscopic Depth Reduction for Combinational Logic Circuits", IECE Technical Rep. EC81-1, Apr. 1981 (in Japanese).
H. Yasuura, "Width and Depth of Combinational Logic Circuits", Information Processing Letters, vol.13, no.4, 5, End, pp.191–194, 1981.
C.E.Leiserson, "Area-Efficiency Graph Layout (for VLSI)", Proc. 21st FOCS, Oct. 1980.
L.G. Valiant, "Universality Considerations in VLSI Circuits", IEEE Trans. on Comput., vol.C-30, no.2, pp.153–157, Feb.1981.
H. Yasuura and S. Yajima, "On Area of Logic Circuits in VLSI", Trans. IECE, vol.J.65-D, pp.1080–1087, Aug. 1982.
T.Sakai, Y.Tsuchida, H.Yasuura, Y.Ooi, Y.Ono, H.Kano, S.Kimura and S.Yajima, "An Interactive Simulation System for Structured Logic Design — ISS", Proc. 19th DA Conf., pp.747–754, June 1982.
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Yajima, S., Yasuura, H. (1983). Hardware algorithms and logic design automation. In: Goto, E., Furukawa, K., Nakajima, R., Nakata, I., Yonezawa, A. (eds) RIMS Symposia on Software Science and Engineering. Lecture Notes in Computer Science, vol 147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-11980-9_21
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DOI: https://doi.org/10.1007/3-540-11980-9_21
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