Abstract
We develop VLSI designs for the solution of several problems that arise in the design rule check phase of design automation.
This research was supported in part by the Office of Naval Research under contract N00014-80-C-0650
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6. References
M. Abramovici, Y. H. Levendel, and P. R. Menon, ”A Logic Simulation Machine” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 65–73
Tom Blank, Mark Stefik, William vanCleemput ”A Parallel Bit Map Processor Architecture for DA Algorithms” ACM IEEE Eighteenth Design Automation Conference Proceedings pp 837–845
Dah-Juh Chyan and Melvin A. Breuer, ”A Placement Algorithm for Array Processors” ACM IEEE 20th Design Automation Conference Proceedings pp 182–188
M. M. Denneau, ”The Yorktown Simulation Engine” CM IEEE Nineteenth Design Automation Conference Proceedings pp 55–59
A. Iosupovici, C. King, and M. Breuer, ”A Module Interchange Machine” ACM IEEE 20th Design Automation Conference Proceedings pp 171–174
R. Kane, S. Sahni, ”A Systolic Design Rule Checker” TR 83-13, Department of Computer Science, University of Minnesota
R. Kane, S. Sahni, ”Systolic Algorithms for Rectilinear Polygons” TR 84-2, Department of Computer Science, University of Minnesota
R. Mane and S. Sahni, ”A hardware algorithm for net extraction”, University of Minnesota, Technical Report, 1984.
E. Kronstadt and G. Pfister, ”Software Support for the Yorktown Simulation Engine” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 60–64
H. T. Kung, ”Let's Design Algorithms for VLSI Systems” Proceedings of the CALTECH Conference on VLSI, January 1979, pp 65–90
H. T. Kung, ”A Listing of Systolic Papers”, Department of Computer Science, Carnegie-Mellon University
C. E. Leiserson, ”Systolic Priority Queues” Proceedings of Conference on VLSI: Architecture, Design, Fabrication California Institute of Tachnology Jan 79 pp 199–214
T. N. Mudge, R. A. Ratenbar, R. M. Lougheed, and D. E. Atkins, ”Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 537–543
R. Nair, S. Jung, S. Liles, and R. Villani, ”Global Wiring on a Wire Routing Machine” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 224–231
G. F. Pflster, ”The Yorktown Simulation Engine, Introduction” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 51–54
L. Seiler, ”A Hardware Assisted Design Rule Check Architecture” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 232–238
Kazuhiro Ueda, Tsutomu Komatsubara and Tsutomu Hosaka, ”A Parallel Processing Approach for Logic Module Placement” ACM IEEE Transactions on Computer Aided Design Vol. CAD-2 No.1 Jan.83 pp 39–47
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Kane, R., Sahni, S. (1984). VLSI systems for design rule checks. In: Joseph, M., Shyamasundar, R. (eds) Foundations of Software Technology and Theoretical Computer Science. FSTTCS 1984. Lecture Notes in Computer Science, vol 181. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-13883-8_77
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DOI: https://doi.org/10.1007/3-540-13883-8_77
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