Abstract
The DIOGENES methodology produces designs for fault-tolerant VLSI processor arrays in two stages: First, the desired array is viewed as an undirected graph and is embedded in a book; then, the book embedding is converted to an efficient fault-tolerant layout of the array. We survey here work on both stages of the methodology, highlighting recent progress and pointing out remaining challenges.
This research was supported in part by NSF Grant DMC-85-04308 and in part by SRC Contract 85-02-054.
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References
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© 1986 Springer-Verlag Berlin Heidelberg
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Rosenberg, A.L. (1986). Diogenes, circa 1986 Ψαχνω για ενα τιμιo ανϑρoπo. In: Makedon, F., Mehlhorn, K., Papatheodorou, T., Spirakis, P. (eds) VLSI Algorithms and Architectures. AWOC 1986. Lecture Notes in Computer Science, vol 227. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16766-8_9
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DOI: https://doi.org/10.1007/3-540-16766-8_9
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