Abstract
We describe a non-uniform deterministic simulation of PRAMs on module parallel computers (MPCs) and on processor networks of bounded degree. The simulating machines have the same number n of processors as the simulated PRAM, and if the size of the PRAM's shared memory is polynomial in n, each PRAM step is simulated by O(log n) MPC steps or by O((log n)2) steps of the bounded-degree network. This improves upon a previous result by Upfal and Wigderson. We also prove an Ω((log n)2/log log n) lower bound on the number of steps needed to simulate one PRAM step on a bounded-degree network under the assumption that the communication in the network is point-to-point.
As an important part of the simulation of PRAMs on MPCs, we use a new technique for dynamically averaging out a given work load among a set of processors operating in parallel.
Part of the research was done while the author was a member of the Mathematical Sciences Research Institute, Berkeley, U.S.A.
This work was supported by the DFG, SFB 124, TP B2, VLSI Entwurf und Parallelität, and by NSF Grant ECS-84-10902.
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© 1987 Springer-Verlag Berlin Heidelberg
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Alt, H., Hagerup, T., Mehlhorn, K., Preparata, F.P. (1987). Deterministic simulation of idealized parallel computers on more realistic ones. In: Albrecht, A., Jung, H., Mehlhorn, K. (eds) Parallel Algorithms and Architectures. Lecture Notes in Computer Science, vol 269. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18099-0_24
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DOI: https://doi.org/10.1007/3-540-18099-0_24
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