Abstract
An architecture which not only elliminates cross referencing but also maintains ordering reservation (suitable for non-equijoin operation) is proposed. The techniques such as parallel processing and pipelining are applied to greatly enhance the system performance. Response time is derived, by comparing the speed of hardware modules, and analyzed for the efficient evaluation of the join operation on the system architecture.
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Liu, Gs., Chen, Hh. (1988). Performance analysis for a join processor. In: Houstis, E.N., Papatheodorou, T.S., Polychronopoulos, C.D. (eds) Supercomputing. ICS 1987. Lecture Notes in Computer Science, vol 297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18991-2_56
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DOI: https://doi.org/10.1007/3-540-18991-2_56
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