Abstract
The design of unrestricted, stuck-at fault tolerant, asynchronous sequential circuits involves the use of complex software. Since software errors might lead to incorrect design, it is important to verify the correctness of the results.
A possible method to do this, is by proving that the design possesses the required properties ’unrestricted’ and ’stuck-at fault tolerant’. This paper presents this approach using the model checker SMV. The approach used is general, and can be applied to all mealy-type asynchronous sequential circuits.
The paper shows the approach using an example. It appears possible to prove that the circuit is unrestricted, does not reach undefined states, is stable, and shows correct behavior. These properties are also proved under the assumption of the presence of one stuck-at fault.
An important intermediate result is the design of the delay in the feedback loop of the asynchronous sequential circuit. Since the duration of the time steps in the model checker is random, it is not possible to use a deterministic model. The model developed is an abstract model for the behavior of delay elements comparable to RC-filters. It includes a notion of synchronization with the other delays in the circuit.
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References
J.F. Meyer: Fault Tolerant Sequential Machines. In: IEEE Transactions on Computers, Vol. c-20, No. 10, October 1971.
Y. Tohma, Y. Ohyama & R. Sakai: Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code. In: IEEE Transactions on Computers, Vol. c-20, No. 11, November 1971.
W.W. Patterson & G.A. Metze: A Fault-Tolerant Asynchronous Sequential Machine, Int. Symp. on Fault Tolerant Computing, p176–81, 1972.
D.K. Pradhan & S.M. Reddy: Fault-Tolerant Asynchronous Networks. In: IEEE Transactions on Computers, Vol. c-22, No. 7, July 1973.
W.W. Patterson & G. Metze: A Fail-Safe Asynchronous Sequential Machine. In: IEEE Transactions on Computers, Vol. c-23, No. 4, April 1974.
D.H. Sawin & G.K. Maki: Asynchronous Sequential Machines Designed for Fault Detection. In: IEEE Transactions on Computers, Vol. c-23, No. 3, March 1974.
G.K. Maki & D.H. Sawin: Fault-Tolerant Asynchronous Sequential Machines. In: IEEE Transactions on Computers, Vol. c-23, No. 7, July 1974.
J.A. Brzozowski & C.-J. H. Seger: Asynchronous Circuits, Monographs in Computer Science, Springer-Verlag, New York, 1995.
P.K. Lala: Fault Tolerant & Fault Testable Hardware Design, Prentice/Hall International, 1985.
E.M. Sentovich e.a.: SIS: A System for Sequential Circuit Synthesis, University of California, Berkeley, Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41, 4 May 1992.
K.L. McMillan: The SMV Language, Cadence Berkeley Labs, 1999.
P.K. Lala: Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers, 2001.
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© 2002 Springer-Verlag Berlin Heidelberg
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van der Meulen, M. (2002). Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV. In: Aagaard, M.D., O’Leary, J.W. (eds) Formal Methods in Computer-Aided Design. FMCAD 2002. Lecture Notes in Computer Science, vol 2517. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36126-X_19
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DOI: https://doi.org/10.1007/3-540-36126-X_19
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