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Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2571))

Abstract

This paper suggests a novel approach to designing aliasing free space compactors with maximal compaction ratio utilizing concepts of strong and weak compatibilities of response data outputs together with conventional switching theory concepts of cover table and frequency ordering for detectable single stuck line faults of the circuit under test (CUT), based on the assumption of generalized sequence mergeability. The advantages of aliasing free space compaction as developed in the paper over earlier techniques are obvious since zero aliasing is achieved here without any modifications of the CUT, while the area overhead and signal propagation delay are relatively less compared to conventional parity tree linear compactors. The approach used works equally well with both deterministic compacted tests and pseudorandom test sets.

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References

  1. Das, S. R., Ramamoorthy, C. V., Assaf, M. H., Petriu, E. M., Jone, W. B.: Fault Tolerance in Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities. IEEE Trans. Instrum. Meas. 50 (2001) 1725–1747.

    Article  Google Scholar 

  2. Bardell, P. H., McAnney, W. H., Savir, J.: Built-In Test for VLSI: Pseudorandom Techniques. Wiley Interscience, New York (1987).

    Google Scholar 

  3. Jone, W. B., Das, S. R.: Space Compression Method for Built-In Self-Testing of VLSI Circuits. Int. J. Comput. Aided VLSI Des. 3 (1991) 309–322.

    Google Scholar 

  4. Karpovsky, M., Nagvajara, P.: Optimal Robust Compression of Test Responses. IEEE Trans. Comput. C-39 (1990) 138–141.

    Article  Google Scholar 

  5. Lee, H. K., Ha, D. S.: On the Generation of Test Patterns for Combinational Circuits. Tech. Rep. 12-93, Dept. Elec. Eng., Virginia Polytec. Inst. and State Univ., Blacksburg, VA (1993).

    Google Scholar 

  6. Li, Y. K., Robinson, J. P.: Space Compression Method with Output Data Modification, IEEE Trans. Comput. Aided Des. 6 ( 1987 ) 290–294.

    Article  Google Scholar 

  7. McCluskey, E. J.: Built-In Self-Test Techniques. IEEE Des. Test Comput. 2 (1985) 21–28.

    Article  Google Scholar 

  8. Pomeranz, I., Reddy, L. N., Reddy, S. M.: COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits. Proc. Int. Test Conf. (1991) 194–203.

    Google Scholar 

  9. Pradhan, D. K., Gupta, S. K.: A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Comput. C-40 (1991) 743–763.

    Article  MathSciNet  Google Scholar 

  10. Reddy, S. M., Saluja, K., Karpovsky, M. G.: Data Compression Technique for Test Responses. IEEE Trans. Comput. C-37 (1988) 1151–1156.

    Article  Google Scholar 

  11. Saluja, K.K., Karpovsky, M.: Testing Computer Hardware Through Compression in Space and Time. Proc. Int. Test Conf. (1983) 83–88.

    Google Scholar 

  12. Savir, J.: Reducing the MISR Size. IEEE Trans. Comput. C-45 (1996) 930–938.

    Article  Google Scholar 

  13. Chakrabarty, K.: Test Response Compaction for Built-In Self-Testing. Ph.D. Dissertation, Dept. Comp. Sc. Eng., Univ. Michigan, Ann Arbor, MI (1995).

    Google Scholar 

  14. Pouya, B. and Touba, N. A.: Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. Proc. VLSI Test Symp. (1998) 70–77.

    Google Scholar 

  15. Rajsuman, R.: System-on-a-Chip: Design and Test. Artech House, Boston, MA (2000).

    Google Scholar 

  16. Das, S.R.: On a New Approach for Finding All the Modified Cut-Sets in an Incompatibility Graph, IEEE Trans. Comput. C-22 (1973) 187–193.

    Article  Google Scholar 

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© 2002 Springer-Verlag Berlin Heidelberg

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Das, S.R., Assaf, M.H., Petriu, E.M., Mukherjee, S. (2002). Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability. In: Das, S.K., Bhattacharya, S. (eds) Distributed Computing. IWDC 2002. Lecture Notes in Computer Science, vol 2571. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36385-8_24

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  • DOI: https://doi.org/10.1007/3-540-36385-8_24

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-00355-7

  • Online ISBN: 978-3-540-36385-9

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